Memory system, memory controller, and method for operating memory system
AssigneeSK hynix Inc.
InventorJeen PARK
Life of this patent
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Abstract
Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.
Claims15
A memory system comprising:
- a memory device;
- and
- a memory controller configured to communicate with the memory device and execute firmware in order to control the memory device,
- wherein the memory controller is further configured to perform an integrity check operation on target code when information indicating whether a supply voltage supplied to the memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage.
A memory controller comprising:
- a memory interface configured to communicate with a memory device;
- and
- a processor configured to communicate with the memory device through the memory interface and execute firmware in order to control the memory device,
- wherein the processor is further configured to perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage.
A method of operating a memory system including a memory device, the method comprising:
- detecting a level of a supply voltage supplied to the memory system through a voltage drop detector;
- receiving, from the voltage drop detector, information indicating whether the supply voltage is maintained at or below a first level for a first unit time;
- and
- performing an integrity check operation on target code.
Dependencies are inferred from the claim text.