Semiconductor memory devices and methods of operating semiconductor memory devices

A semiconductor memory device comprising:

• a memory cell array including a plurality of row blocks, wherein each of the plurality of row blocks is connected to a word-line and includes a plurality of segments including at least one dynamic memory cell;
• a row decoder configured to receive a row address corresponding to a first word-line connected to a first row block of the plurality of row blocks and, in response to the row address, activate the first word-line and a second word-line connected to a second row block of the plurality of row blocks based on first fuse information indicating that the second row block is mapped to the first row block;
• and
• a column decoder configured to receive a column address corresponding to a bit-line connected to a first segment of the first row block and a second segment of the second row block and, in response to the column address, access the second segment connected to the activated second word-line based on second fuse information indicating that the first segment is repaired.

A semiconductor memory device comprising:

• a memory cell array including a plurality of row blocks, wherein each of the plurality of row blocks is connected to a word-line and includes a plurality of segments including at least one dynamic memory cell;
• a row decoder configured to receive a row address corresponding to a first word-line connected to a first row block of the plurality of row blocks and, in response to the row address, activate the first word-line and a second word-line connected to a second row block of the plurality of row blocks based on first fuse information indicating that the second row block is a slave row block of the first row block;
• a column decoder configured to receive a column address corresponding to a bit-line connected to a first segment of the first row block and a second segment of the second row block and, in response to the column address, access the second segment connected to the activated second word-line based on second fuse information indicating that the first segment is repaired;
• and
• a peripheral circuit configured to control the row decoder and the column decoder based on a command and an address received from an outside, the address including the row address and the column address.

A method of operating a semiconductor memory device,

• wherein the semiconductor memory device includes a memory cell array with a plurality of row blocks, wherein each of the plurality of row blocks is connected to a word-line and includes a plurality of segments including at least one dynamic memory cell,
• the method comprising:
• receiving a row address corresponding to a first word-line connected to a first row block of the plurality of row blocks;
• activating, in response to the row address, the first word-line and a second word-line connected to a second row block of the plurality of row blocks based on first fuse information indicating that the second row block is mapped to the first row block;
• receiving a column address corresponding to a bit-line connected to a first segment of the first row block and a second segment of the second row block;
• and
• accessing, in response to the column address, the second segment connected to the activated second word-line based on second fuse information indicating that the first segment is repaired.