Anti-fuse memory cell state detection circuit and memory
AssigneeChangxin Memory Technologies, Inc.
InventorRumin JI
Life of this patent
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Abstract
A state detection circuit of an anti-fuse memory cell includes a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller; an anti-fuse memory cell array including a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller; and a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage.
Claims10
A state detection circuit of an anti-fuse memory cell, comprising:
- a first switching element, having a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller;
- an anti-fuse memory cell array comprising a plurality of anti-fuse memory cell sub-arrays, bit lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the first node, and word lines of the plurality of anti-fuse memory cell sub-arrays being all connected to the controller;
- and
- a comparator, having a first input end connected to the first node, and a second input end connected to a reference voltage;
- wherein the anti-fuse memory cell sub-array comprises a plurality of anti-fuse memory cells;
- and the controller is configured to detect states of the plurality of anti-fuse memory cells one by one by switching on or off the first switching element.
Dependencies are inferred from the claim text.