US 2022/0020436 A1Published application

Semiconductor memory device

AssigneeSK hynix Inc.

InventorsHyung Jin CHOI, Sung Hyun HWANG

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells for storing data;
a page buffer connected to at least one of the plurality of memory cells through a bit line and configured to read the data stored in the memory cell;
control logic configured to generate a plurality of control signals for controlling an operation of the page buffer;
and
a voltage generator configured to generate activation voltages of the plurality of control signals,
wherein the page buffer comprises:
a first transistor connected between the bit line and a first node;
a second transistor connected between a power voltage and a second node;
a third transistor connected between the first node and the second node;
a fourth transistor connected between the second node and a third node;
and
a fifth transistor connected between the first node and the third node, and
wherein the voltage generator is further configured to control an activation voltage of a first control signal controlling the fifth transistor among the plurality of control signals based on temperature of the semiconductor memory device.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/097,893Filed 13 Nov 2020
Priority: KR 10-2020-008892317 Jul 2020
Published: 20 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 7/04
Arrangements for writing information into, or reading information out from, a digital store: with means for avoiding disturbances due to…
G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
G11C 16/3459
Arrangements for verifying correct programming or for detecting overprogrammed cells: circuits or methods to verify correct programming of…