Multiplexed memory device interface and method
AssigneeMicron Technology, Inc.
InventorsAparna U. Limaye, Timothy Mowry Hollis
Life of this patent
Estimating the term…
Abstract
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.
Claims26
A memory device, comprising:
- a buffer including a host device interface, and a DRAM interface;
- one or more DRAM dies;
- a multiplexer circuit coupled between the one or more DRAM dies and the DRAM interface;
- and
- circuitry in the buffer, configured to operate the host interface at a first data speed, and to operate the DRAM interface at a second data speed, slower than the first data speed.
A memory system, comprising:
- two or more memory devices, each memory device including:
- a buffer coupled to a substrate, the buffer including a host device interface, and a DRAM interface;
- one or more DRAM dies supported by the substrate;
- multiple wire bond interconnections between the DRAM interface of the buffer and the one or more DRAM dies;
- circuitry in the buffer, configured to operate the host interface at a first data speed, and to operate the DRAM interface at a second data speed, slower than the first data speed;
- and
- a multiplexer circuit coupled between a host controller and the host interfaces of the two or more memory devices.
A system, comprising:
- a processor coupled to a first substrate;
- a memory device coupled to the first substrate adjacent to the processor, the memory device including:
- a buffer including a host device interface, and a DRAM interface;
- one or more DRAM dies;
- a multiplexer circuit coupled between the one or more DRAM dies and the DRAM interface;
- and
- circuitry in the buffer, configured to operate the host interface at a first data speed, and to operate the DRAM interface at a second data speed, slower than the first data speed.
A method of operating a memory device, comprising:
- exchanging data between a processor and a buffer at a first data speed;
- exchanging data between the buffer and a multiplex circuit at a second speed, slower than the first speed;
- and
- multiplexing the data between the buffer and two or more DRAM die stacks.
Dependencies are inferred from the claim text.