Sensing circuit and method for multi-level memory cell

A sensing circuit connected with a selected memory cell, the sensing circuit comprising:

• a cell clock generator receiving a cell current from the selected memory cell, and converting the cell current into a cell clock signal, wherein the selected memory cell is a multi-level memory cell;
• a reference clock generator receiving a reference current, and converting the reference current into a reference clock signal;
• a counter receiving the cell clock signal, and generating a count value;
• a latching signal generator receiving the reference clock signal, wherein when a pulse number of the reference clock signal reaches a predetermined count value, the latching signal generator activates a latching signal;
• a latch receiving the count value and the latching signal, wherein when the latching signal is activated, the latch issues a latched count value;
• and
• a count-to-state conversion circuit receiving the latched count value, and issuing a state value, wherein a storage state of the selected memory cell is determined according to the state value.