Memory device and method for input and output buffer control thereof
AssigneeWinbond Electronics Corp.
InventorShinya Fujioka
Life of this patent
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Abstract
A memory device and a method for input/output buffer control are provided. The memory device includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input/output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to an operation mode of the memory device, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.
Claims13
A memory device comprising:
- a pseudo static random access memory comprising an input/output circuit having a fast mode circuit and a slow mode circuit;
- and
- a controller coupled to the pseudo static random access memory and configured to adjust a power supply voltage and a clock frequency according to an operation mode of the memory device, and generate a register setting code based on an adjusted power supply voltage and an adjusted clock frequency, wherein
- the pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.
A method for input/output buffer control adapted for a memory device, wherein the memory device comprises a pseudo static random access memory and a controller, the pseudo static random access memory comprises an input/output circuit having a fast mode circuit and a slow mode circuit, and the method for input/output buffer control comprises:
- adjusting a power supply voltage and a clock frequency according to an operation mode of the memory device;
- generating a register setting code based on an adjusted power supply voltage and an adjusted clock frequency;
- and
- enabling one of the fast mode circuit and the slow mode circuit according to the register setting code, and disabling the other of the fast mode circuit and the slow mode circuit.
Dependencies are inferred from the claim text.