Processor, logic chip and method for binarized convolution neural network

A logic chip for implementing a binarized convolutional neural network (BCNN), the logic chip comprising:

• a shared logic module that is capable of performing both a binarized convolution operation and a down-sampling operation on a feature map;
• a memory storing adjustable parameters of the shared logic module, wherein the adjustable parameters determine whether the shared logic module performs a binarized convolution operation or a down-sampling operation;
• and
• a controller or a control interface to control the shared logic module to perform at least one binarized convolution operation followed by at least one down-sampling operation by adjusting the adjustable parameters of the shared logic module.

A method of classifying an image by a processor implementing a binarized convolution neural network, the method comprising:

• a) receiving, by the processor, a first feature map corresponding to an image to be classified;
• b) receiving, by the processor, a first set of parameters including at least one filter, at least one stride and at least one augmentation variable;
• c) performing, by the processor, a binarized convolution operation on the input feature map using the at least one filter and at least one stride to produce a second feature map;
• d) performing, by the processor, an augmentation operation on the input feature map using the at least one augmentation variable to produce a third feature map;
• e) combining, by the processor, the second feature map and the third feature map;
• f) receiving a second set of parameters including at least one filter, at least one stride and at least one augmentation variable;
• g) repeating c) to e) using the second set of parameters in place of the first set of parameters and the combined second and third feature maps in place of the first feature map.