Tamper resistant obfuscation circuit

An obfuscation circuit comprising:

• a first integrated circuit structure having a tamper-resistant nonvolatile memory which encodes at least one obfuscation function, and having wiring which connects said tamper-resistant nonvolatile memory to output pads;
• and
• a second integrated circuit structure having a semiconductor substrate with a plurality of logic cells formed therein, at least some of said logic cells being part of a logic circuit, said second integrated circuit structure including wiring which interconnects one or more logic cells of said logic circuit with a plurality of input pads, wherein said first integrated circuit structure is attached to said second integrated circuit structure such that said input pads of said second integrated circuit structure are operatively connected to said output pads of said first integrated circuit structure.

An integrated circuit package comprising:

• an integrated circuit having a plurality of logic circuits which are controlled by logic signals to operate on operand data values;
• and
• at least one Boolean function encoded in a tamper-resistant nonvolatile memory wherein said Boolean function obfuscates one or more of the logic signals, obfuscates one or more of the operand data values, and selectively releases at least one of said logic circuits by enabling a power-up signal for said at least one logic circuit in response to a corresponding release key.