Routing in a Network of Processors

A processor configured to be interconnected in a network of processors, the processor comprising:

• a plurality of processing units arranged on a chip, each processing unit configured to execute program code;
• an on-chip interconnect arranged to enable exchange of data between the processing units;
• a plurality of external interfaces configured to communicate data off chip as packets having destination addresses, a first one of the external interfaces being configured to be connected by a first one of the external links to a first additional processor of the network and a second one of the external interfaces being configured to be connected by a corresponding external link to a second additional processor of the network;
• a routing bus configured to route the packets between the processing units and the first external interface and the second external interface;
• and
• a routing register defining a routing domain for the processor, the routing domain comprising at least one of the first additional processor and the second additional processor, and at least a subset of further additional processors of the network, wherein the further additional processors are directly or indirectly connected to the processor.