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US 2022/0019442 A1Published application
Reconfigurable processing-in-memory logic using look-up tables
AssigneeMicron Technology, Inc.
InventorDmitri Yudanov
Life of this patent
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Abstract
An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.
Claims17
A system, comprising:
- a memory array to store a plurality of look-up tables (LUTs) and data;
- a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs;
- and
- a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data;
- wherein the control block controls the logic array and the plurality of LUTs to implement a computational pipeline of systolic arrays.
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6-9. (canceled)
A system-on-chip (SoC), comprising:
- a memory array to store a plurality of look-up tables (LUTs) and data;
- one or more logic arrays coupled to the memory array, the one or more logic arrays to:
- control a computational pipeline of systolic arrays by activating one or more LUTs of the plurality of LUTs;
- and
- perform logic operations on the activated LUTs and the data.
2 more elements
A method, comprising:
- storing, in a memory array, a plurality of look-up tables (LUTs) and data;
- activating, by a control block coupled to the memory array, one or more LUTs of the plurality of LUTs;
- performing, by a logic array coupled to the control block and to the memory array, based on control inputs received from the control block, logic operations on the activated LUTs and the data;
- and
- implementing, by the control block controlling the logic array and the plurality of LUTs, a computational pipeline of systolic arrays.
2 more elements
Dependencies are inferred from the claim text.