In-memory computation circuit and method

A method of operating a memory circuit, the method comprising:

• receiving, at a column of memory cells, a set of kth bits of a number H of bits of each input data element of a plurality of input data elements;
• using each memory cell of the column of memory cells to multiply the kth bit of a corresponding input data element of the plurality of data elements with a first weight data element stored in the memory cell, thereby generating a corresponding first product data element;
• and
• using an adder tree to generate a summation data element based on each of the first product data elements.

A memory circuit comprising:

• a selection circuit configured to, for a plurality of input data elements comprising H bits each, sequentially output selected sets of kth bits to corresponding memory cells of each column of memory cells of a plurality of columns of memory cells;
• a plurality of adder trees, each adder tree of the plurality of adder trees being coupled to a corresponding column of memory cells of the plurality of columns of memory cells;
• and
• a plurality of accumulators, each accumulator of the plurality of accumulators being coupled to a corresponding adder tree of the plurality of adder trees,
• wherein
• each memory cell of each column of memory cells comprises a multiplier configured to generate a product data element based on the corresponding kth bit of the selected set of kth bits and a weight data element stored in the memory cell,
• each adder tree of the plurality of adder trees is configured to generate, for each sequentially output set of kth bits, a summation data element based on each of the product data elements of the corresponding column of memory cells, and
• each accumulator of the plurality of accumulators is configured to generate a partial sum based on the summation data elements generated by the corresponding adder tree of the plurality of adder trees.