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US 2022/0019276 A1Published application
Power Management by Clock Dithering
AssigneeGraphcore Limited
InventorIan Malcolm KING
Life of this patent
Estimating the term…
Abstract
A system and method for docking a processing unit provided. According to the method, the system dithers between the two signals provided by the two clock generators so as to clock the processing unit at an average clock frequency having a value between the frequencies of the two signals. The average clock frequency is adjusted by modifying the proportion of time spent on one clock signal vs the other clock signal.
Claims27
A method of controlling a frequency of a clock signal for a processing unit, the method comprising:
- cycling between selection of:
- a first clock generator for providing a processing unit clock signal for executing an application during a first part of a cycle;
- and
- a second clock generator for providing the processing unit clock signal for executing the application during a second part of the cycle, wherein a frequency of the clock signal provided by the second clock generator is less than a frequency of the clock signal provided by the first clock generator,
- increasing an average clock frequency for the processing unit by increasing a ratio between a duration of the first part of the cycle and a duration of the second part of the cycle;
- and
- decreasing the average clock frequency for the processing unit by decreasing the ratio between the duration of the first part of the cycle and the duration of the second part of the cycle.
4 more elements
A system for providing a processing unit clock signal to a processing unit, the system comprising:
- a first clock generator configured to provide the processing unit clock signal for executing an application during a first part of a cycle;
- a second clock generator configured to provide the processing unit clock signal for executing the application during a second part of the cycle, wherein a frequency of the processing unit clock signal provided by the second clock generator is less than a frequency of the processing unit clock signal provided by the first clock generator;
- and
- switching circuitry configured to:
- switch between selecting the first clock generator for clocking the processing unit during a first part of the cycle and the second clock generator for clocking the processing unit during a second part of the cycle;
- and
- increase an average clock frequency for the processing unit by increasing a ratio between a duration of the first part of the cycle and a duration of the second part of the cycle.
4 more elements
A method comprising:
- executing an application by a processing unit, the processing unit receiving a processing unit clock signal;
- performing a plurality of cycles of the processing unit clock signal, and within each cycle controlling a multiplexor to switch between:
- a first clock generator in a first cycle part and a second clock generator in a second cycle part, wherein a frequency of the second clock generator is less than a frequency of the first clock generator;
- increasing an average value of the processing unit clock signal, including increasing a ratio between a duration of the first cycle part and a duration of the second cycle part;
- and
- decreasing the average value of the processing unit clock signal, including decreasing the ratio between the duration of the first cycle part and the duration of the second cycle part.
3 more elements
Dependencies are inferred from the claim text.