Delay calibration for a stepped frequency continuous wave digital signal chain

A method for operating a stepped frequency continuous wave (SFCW) system, the method comprising:

• receiving a SFCW signal comprising a plurality of consecutive bursts, each burst comprising a pulse of a different frequency;
• receiving a trigger indicative of a time when the SFCW signal was transmitted;
• for each burst of the SFCW signal:
• resetting an oscillator based on the received trigger and further based on an oscillator delay,
• generating a downconverted signal by performing a frequency downconversion of a digital signal that includes a sequence of digital samples indicative of the burst using an oscillator signal generated by the oscillator after the oscillator has been reset,
• selecting a subset of S consecutive digital samples of the downconverted digital signal based on the trigger and a moving averager delay,
• using the moving averager to compute a moving average for the selected subset of S consecutive digital samples, and
• providing the computed moving average to a baseband circuit for determining one or more of an amplitude and a phase for the burst.

A stepped frequency continuous wave (SFCW) system configured to receive a SFCW signal comprising K bursts, where K is an integer greater than 1 and where each burst includes a pulse of a different frequency, the system comprising a channel that includes:

• an analog-to-digital converter (ADC);
• 2K downconverters, each configured to receive a signal indicative of an output of the ADC;
• 2K moving averagers, each configured to receive a signal indicative of an output of a different one of the 2K downconverters;
• and
• a calibration circuit, configured to:
• enable the ADC to receive a signal indicative of a burst with a test pulse, the burst having a time duration of L clock cycles, and to generate a digital signal that includes a sequence of digital samples indicative of the burst,
• enable one of the 2K downconverters to generate a downconverted digital signal by performing a frequency downconversion of the digital signal generated by the ADC,
• receive a trigger indicative of a time when the burst was transmitted,
• enable one or more of the 2K moving averagers to compute a moving average of a subset of S consecutive digital samples of the downconverted digital signal for each clock cycle for the time duration of L clock cycles,
• determine an amplitude for each computed moving average,
• identify one of the computed moving averages for which the determined amplitude is closest to an expected amplitude,
• identify a clock cycle of the identified moving average, and
• update at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle.