Method for manufacturing thin film transistor, and display panel

A method for manufacturing a thin film transistor, comprising:

• forming a gate metal layer on a surface of the substrate by using a first photomask process;
• sequentially forming a gate insulation layer and an intrinsic amorphous silicon thin film layer on the gate metal layer:
• forming an etching barrier layer on an intrinsic amorphous silicon layer by using a second photomask process;
• forming a doped amorphous silicon thin film layer on the etching barrier layer, wherein the doped amorphous silicon thin film layer overlays the etching barrier layer, and the intrinsic amorphous silicon thin film layer outside a region overlaid by the etching barrier layer;
• forming the intrinsic amorphous silicon layer and a doped amorphous silicon layer by using a third photomask process, and a channel corresponding to the surface of the etching barrier layer is formed on the doped amorphous silicon layer;
• forming a protection layer that overlays the channel by using a fourth photomask process;
• forming a metal seed layer made of a nickel disilicide material on the amorphous silicon layer;
• converting the intrinsic amorphous silicon layer into an intrinsic polysilicon layer under an induction effect of the metal seed layer and through an annealing treatment, converting the doped amorphous silicon layer into a doped polysilicon layer under an induction effect of the metal seed layer and through an annealing treatment;
• forming a source and a drain on the doped polysilicon layer by using a fifth photomask process;
• and
• forming an insulation interlayer on the source and the drain, wherein
• a temperature range of the annealing-crystallization is between 400° C. and 600° C., and a time range of the annealing-crystallization is between 0.5 h and 2 h.

A display panel, comprising a plurality of scanning lines, a plurality of data lines, a plurality of pixel electrodes, and a plurality of active switches, wherein each active switch is a thin film transistor, and the thin film transistors each comprise:

• a substrate;
• and
• sequentially forming a gate metal layer, a gate insulation layer, a polysilicon layer, a source and a drain on the substrate;
• the source of the thin film transistor is connected to the data lines, a gate is connected to the scanning lines, and the drain is connected to the pixel electrodes;
• wherein
• the polysilicon layer is made by using the following method:
• forming an amorphous silicon layer on the gate insulation layer;
• forming a metal seed layer on the amorphous silicon layer, the metal seed layer being made from nickel disilicide material;
• and
• converting the amorphous silicon layer into the polysilicon layer under an induction effect of the metal seed layer and through an annealing treatment.