Field effect transistors with negative capacitance layers
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChansyun David Yang, Chan-Lon Yang, Keh-Jeng Chang
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Abstract
The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.
Claims20
A method, comprising:
- forming a fin structure including a fin base portion and a stacked fin portion on a substrate, wherein the stacked fin portion comprises a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers;
- replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer, wherein the NC layer comprises an NC dielectric material;
- and
- forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer.
A method, comprising:
- forming a fin structure with a fin base portion and a stacked fin portion on a substrate, wherein the stacked fin portion comprises a first set of semiconductor layers on the fin base portion, a second set of semiconductor layers above the first set of semiconductor layers, and a sacrificial semiconductor layer between the first and second sets of semiconductor layers;
- forming a first negative capacitance (NC) dielectric structure at a first region of the sacrificial semiconductor layer, wherein the first NC dielectric structure comprises a first NC dielectric material;
- forming an inner spacer structure adjacent to a first side of the first NC dielectric structure;
- forming an epitaxial source/drain (S/D) region on the fin structure and adjacent to the inner spacer structure;
- filling a second NC dielectric structure at a second region of the sacrificial semiconductor layer, wherein:
- the second region is adjacent to the first region of the sacrificial semiconductor layer;
- the second NC dielectric structure comprises a second NC dielectric material;
- and
- the second NC dielectric structure is adjacent to a second side of the first NC dielectric structure;
- and
- forming gate electrodes around the first NC dielectric structure, the second NC dielectric structure, the first set of semiconductor layers, and the second set of semiconductor layers.
A semiconductor device, comprising:
- a fin structure with a fin base portion and a stacked fin portion on a substrate, wherein the stacked fin portion comprises a first semiconductor layer on the fin base portion and a second semiconductor layer above the first semiconductor layer;
- a negative capacitance (NC) layer between the first and the second semiconductor layers, wherein the NC layer comprises an NC dielectric material;
- first and second gate dielectric layers wrapped around the first and second semiconductor layers, respectively, and in contact with the NC layer;
- and
- gate electrodes wrapped around the first semiconductor layer, the second semiconductor layer, and the NC layer.
Dependencies are inferred from the claim text.