Semiconductor device

A semiconductor device comprising:

• a substrate;
• an active pattern extending in a first direction on the substrate;
• a gate electrode extending in a second direction on the active pattern, the second intersecting the first direction;
• a gate spacer extending in the second direction along side walls of the gate electrode;
• an interlayer insulating layer contacting side walls of the gate spacer;
• a trench formed on the gate electrode in the interlayer insulating layer;
• a first capping pattern provided along walls of the trench, the first capping pattern including silicon oxycarbide (SiOC), and including carbon of a first atomic ratio;
• and
• a second capping pattern provided on the first capping pattern in the trench, the second capping pattern including silicon oxycarbide (SiOC), and including carbon of a second atomic ratio that is smaller than the first atomic ratio.

A semiconductor device comprising:

• a substrate;
• an active pattern extending in a first direction on the substrate;
• a gate electrode extending in a second direction on the active pattern, the second direction intersecting the first direction;
• a gate spacer extending in the second direction along side walls of the gate electrode;
• an interlayer insulating layer contacting side walls of the gate spacer;
• a trench formed on the gate electrode in the interlayer insulating layer;
• a first capping pattern provided along side walls of the trench, the first capping pattern comprises a first side wall and a second side wall opposite to the first side wall, the first side wall has an inclined profile, the second side wall contacting the interlayer insulating layer, and the first capping pattern including silicon oxycarbide (SiOC);
• a second capping pattern provided on the first capping pattern in the trench, the second capping pattern contacting the first side wall of the first capping pattern, the second capping pattern including a material different from a material of the first capping pattern;
• a source/drain region provided on at least one of side of the gate electrode;
• and
• a source/drain contact penetrating the interlayer insulating layer in a third direction that is perpendicular to the first direction and the second direction, the source/drain contact being connected to the source/drain region.