US 2022/0013647 A1Published application

Termination structures for trench-gate field-effect transistors

AssigneeSemiconductor Components Industries, LLC

InventorsTakashi OGURA, Takashi HIROSHIMA, Toshimitsu TANIGUCHI

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Abstract

In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate, e.g., an n-type semiconductor region, epitaxial layer, etc.).

Claims20

Dependent claims

A trench-gate field-effect transistor (trench-FET) comprising:

a semiconductor region of a first conductivity type;
a plurality of trenches defined within the semiconductor region, the plurality of trenches being arranged in parallel with one another;
an active region including a portion of a first trench of the plurality of trenches;
and
a termination region at least partially surrounding the active region, the termination region including:
a second trench of the plurality of trenches, the second trench being disposed at an end of the plurality of trenches;
and
a termination extension of the first conductivity type disposed adjacent to the second trench, the termination extension excluding a trench, and excluding an implant of a second conductivity type opposite the first conductivity type,
the portion of the first trench having:
a dielectric material of a first thickness disposed on a bottom surface, a lower portion of a first sidewall, and a lower portion of a second sidewall of the first trench, the second sidewall being opposite the first sidewall;
and
a dielectric material of a second thickness disposed on an upper portion of the first sidewall and an upper portion of the second sidewall, the first thickness being greater than the second thickness;
and
the second trench having the dielectric material of the first thickness disposed on a bottom surface and a first sidewall, the first sidewall of the second trench being adjacent to the termination extension.

11 more elements

A trench-gate field-effect transistor (trench-FET) comprising:

a semiconductor region of a first conductivity type;
a plurality of trenches defined within the semiconductor region, the plurality of trenches being arranged in parallel with one another;
an active region including a first portion of a first trench of the plurality of trenches;
and
a termination region at least partially surrounding the active region, the termination region including:
a second portion of the first trench;
and
a third portion of the first trench, the first portion of the first trench being disposed between the second portion of the first trench and the third portion of the first trench;
and
a termination extension of the first conductivity type disposed in the semiconductor region, the termination extension including:
a first portion adjacent to the second portion of the first trench;
and
a second portion adjacent to the third portion of the first trench,
the first trench being disposed between the first portion of the termination extension and the second portion of the termination extension, and
the termination extension excluding a trench, and excluding an implant of a second conductivity type opposite the first conductivity type,
the first portion of the first trench having:
a dielectric material of a first thickness disposed on a bottom surface, a lower portion of a first sidewall, and a lower portion of a second sidewall of the first trench, the second sidewall being opposite the first sidewall;
and
a dielectric material of a second thickness disposed on an upper portion of the first sidewall and an upper portion of the second sidewall, the first thickness being greater than the second thickness;
and
the second portion and the third portion of the first trench having the dielectric material of the first thickness disposed on respective bottom surfaces, respective first sidewalls and respective second sidewalls of the first trench.

18 more elements

A trench-gate field-effect transistor (trench-FET) comprising:

a semiconductor region of a first conductivity type;
a plurality of trenches defined within the semiconductor region, the plurality of trenches being arranged in parallel with one another;
an active region including a portion of a first trench of the plurality of trenches;
and
a termination region at least partially surrounding the active region, the termination region including:
a second trench of the plurality of trenches, the second trench being disposed at an end of the plurality of trenches;
and
a termination extension of the first conductivity type disposed adjacent to the second trench, the termination extension excluding a trench, and excluding an implant of a second conductivity type opposite the first conductivity type,
the portion of the first trench having:
a dielectric material of a first thickness disposed on a bottom surface, a lower portion of a first sidewall, and a lower portion of a second sidewall of the first trench, the second sidewall being opposite the first sidewall;
and
a dielectric material of a second thickness disposed on an upper portion of the first sidewall and an upper portion of the second sidewall, the first thickness being greater than the second thickness;
the second trench having the dielectric material of the first thickness disposed on a bottom surface, a first sidewall and a second sidewall of the second trench, the first sidewall of the second trench being adjacent to, and in contact with the termination extension, the second sidewall of the second trench being opposite the first sidewall of the second trench;
a third trench of the plurality of parallel arranged trenches that is adjacent to the first trench, the active region further including a portion of the third trench, the third trench being disposed between the first trench and the second trench;
and
a polysilicon layer disposed on the termination extension, over the second trench and over the third trench, an edge of the polysilicon layer being disposed on a semiconductor mesa defined between the first trench and the third trench.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/948,793Filed 1 Oct 2020
Priority: 9 Jul 2020
Published: 13 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/665
Vertical dmos [vdmos] fets: having edge termination structures
H10D 64/516
Characterised by the insulating layers: the thicknesses being non-uniform
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors