Semiconductor device and chip singulation method

A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable, the semiconductor device comprising:

• a semiconductor layer that includes:
• a semiconductor substrate that contains an impurity of a first conductivity type;
• and
• a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate, the low-concentration impurity layer containing an impurity of the first conductivity type having a concentration lower than a concentration of the impurity of the semiconductor substrate;
• a metal layer in contact with an entirety of an undersurface of the semiconductor substrate, the metal layer having a thickness of at least 10 μm;
• a first vertical metal-oxide semiconductor (MOS) transistor in a first region of the semiconductor layer;
• a second vertical MOS transistor in a second region of the semiconductor layer, the second region being adjacent to the first region in a plan view of the semiconductor layer;
• and
• a protective layer covering at least a portion of an upper surface of the semiconductor layer,
• wherein the semiconductor substrate functions as a common drain region for the first vertical MOS transistor and the second vertical MOS transistor,
• a side surface of the metal layer includes roughness that forms vertical stripes extending in a vertical direction that is a direction perpendicular to the metal layer, the roughness having a maximum height of profile greater than 1.0 μm, the maximum height of profile being measured in a lateral direction, and
• in a plan view of the semiconductor device, an area occupancy of a formation containing metal included in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, the 10-μm square region being included in an upper surface of the semiconductor device.