Carrier injection control fast recovery diode structures and methods of fabrication

A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:

• forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising:
• a medium level doped buffer region on the top region of the drift region,
• a lightly doped middle region, and
• a medium level doped field stop region;
• forming trenches, in the drift region, having depth ranging from 2-6 microns;
• ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
• filling trenches with a dielectric layer encircling medium level doped buffer region of the drift region;
• forming a shallow and lightly doped junction anode region of the second conductivity type;
• depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;
• depositing a frontside metal and passivation layer;
• and
• grinding a FRD wafer backside and etching to thin the wafer and depositing backside metal Titanuim:Nickel:Silver (Ti:Ni:Ag) alloy or gold (Au) to form at least an anode electrode;
• wherein the first conductivity type is N type and the second conductivity type is P type.

A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:

• forming a drift region of a first conductivity type on top of a lightly doped semiconductor substrate, the drift region supporting blocking of high voltage and comprising:
• a buffer region on the top region of the drift region,
• a lightly doped middle region, and
• a medium level doped field stop region;
• forming trenches, in the drift region, having depth ranging from 2-6 microns;
• ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
• filling trenches;
• forming a shallow junction anode region of the second conductivity type;
• depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;
• depositing a frontside metal and passivation layer;
• grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness;
• sputtering N+ silicon or N+ poly S as a cathode to a whole or certain portion of the wafer backside, depositing a dielectric layer to the wafer backside, wherein cathode contacts are opened via a mask before the sputtering of the N+ Silicon or N+ poly Si;
• and
• depositing metal Ti:Ni:Ag or Au to the wafer backside and sintering for completing fabrication of the wafer for the FRD;
• wherein the first conductivity type is N type and the second conductivity type is P type.

A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:

• forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising:
• a medium level doped buffer region on the top region of the drift region,
• a lightly doped middle region, and
• a medium level doped field stop region;
• forming trenches, in the drift region, having depth ranging from 2-6 microns;
• ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;
• filling trenches with poly silicon of the second conductivity type formed by ion implantation surrounding two or all sides of the medium level doped buffer region;
• an anode electrode electrically in contact with the second conductivity type poly silicon filling the trenches;
• varying the doping concentration of the poly silicon filling the trenches to control, at least in part, the carrier injection and resulting reverse recovery time of the FRD;
• depositing a BPSG or PSG for defining contact regions;
• depositing metal and passivation layer;
• and
• grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness and depositing backside metal Ti:Ni:Ag alloy or Au.