US 2022/0013581 A1 · VARIABLE RESISTANCE MEMORY DEVICE

Abstract

A variable resistance memory device includes lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction, peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction, and lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction. Each of the lower conductive lines includes a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion connecting the first lower extending portion to the second lower extending portion. Each of the lower contacts is in the lower connecting portion of a respective one of the lower conductive lines.

Claims27

Dependent claims

A variable resistance memory device comprising:

lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction;
peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction;
and
lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction,
wherein each of the lower conductive lines comprises a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion that couples the first lower extending portion to the second lower extending portion, and
wherein each of the lower contacts is on the lower connecting portion of a respective one of the lower conductive lines.

3 more elements

A variable resistance memory device comprising:

a peripheral circuit unit on a substrate and comprising peripheral transistors;
and
a first cell stack and a second cell stack sequentially stacked on the peripheral circuit unit in a first direction,
wherein the first cell stack comprises a first lower conductive line including a first lower extending portion that extends in a second direction crossing the first direction, a second lower extending portion that is offset in a third direction crossing the first direction and the second direction from the first lower extending portion and extends in the second direction, and a first lower connecting portion that couples the first lower extending portion to the second lower extending portion, and
a first lower contact that electrically connects the first lower conductive line to at least one of the peripheral transistors and extends in the first direction,
wherein the first lower contact is on the first lower connecting portion.

3 more elements

A variable resistance memory device comprising:

a peripheral circuit unit on a substrate and comprising peripheral transistors;
and
a first cell stack and a second cell stack sequentially stacked on the peripheral circuit unit in a first direction,
wherein the first cell stack comprises a first lower conductive line including a first lower extending portion that extends in a second direction crossing the first direction, a second lower extending portion that is offset in a third direction crossing the first direction and the second direction from the first lower extending portion and extends in the second direction, and a first lower connecting portion that couples the first lower extending portion to the second lower extending portion,
a first lower contact that electrically connects the first lower conductive line to at least one of the peripheral transistors and extends in the first direction,
a first upper conductive line comprising a first upper extending portion that extends in the third direction, a second upper extending portion that is offset in the second direction from the first upper extending portion and extends in the third direction, and a first upper connecting portion that couples the first upper extending portion to the second upper extending portion, and
a first upper contact that electrically connects the first upper conductive line to at least one of the peripheral transistors and extends in the first direction,
wherein the first lower contact is on the first lower connecting portion, and
the first upper contact is on the first upper connecting portion.

6 more elements

Dependencies are inferred from the claim text.

Variable resistance memory device

Life of this patent

Variable resistance memory device

Life of this patent

Abstract

Claims27