Isolation structure for suppression floating diffusion junction leakage in cmos image sensor

A pixel array for a CMOS image sensor, comprising:

• a semiconductor substrate having a front side and a back side;
• a plurality of pixel cells formed in the semiconductor substrate, each pixel cell including a pixel region having at least one photosensitive element and a pixel transistor region disposed adjacent the pixel region, the pixel transistor region comprising
• at least one floating diffusion region, at least one transistor gate, and drain/source regions each having a first conductive type;
• a doped well region disposed in the semiconductor substrate beneath the at least one transistor gate and surrounding the drain/source regions and the at least one floating diffusion region, the dope well region having a second conductive type that is different from the first conductive type of the drain/source regions;
• a first shallow trench isolation structure in the front side of the semiconductor substrate and extending around the perimeter of the pixel transistor region;
• and
• a first deep trench isolation structure in the back side of the semiconductor substrate, wherein the first back side deep trench isolation structure extends a first depth into the semiconductor substrate and abuts against the first shallow trench isolation structure,
• wherein the first deep trench isolation structure together with the first shallow trench isolation structure isolates the pixel transistor region from the pixel region by encapsulating the doped well region.

A method for fabricating a pixel array, comprising:

• forming a semiconductor substrate having a front side and a back side and including a one or more pixel cells each having a pixel region and a pixel transistor region, the pixel transistor region comprising
• at least one floating diffusion region, at least one transistor gate, and drain/source regions having a first conductive type;
• a doped well region disposed in the semiconductor substrate below the at least one transistor gate and surrounding the drain/source regions and the floating diffusion region, the doped well region having a second conductive type different from the first conductive type;
• and
• a shallow trench isolation structure in a front side of the semiconductor substrate that extends around the perimeter of the pixel transistor region;
• forming, for each pixel transistor region, a first deep trench in the back side of the semiconductor substrate that surrounds the pixel transistor region;
• lining each first deep trench with a dielectric material to form first lined deep trenches;
• filling, from the back side of the semiconductor substrate, the first lined deep trenches with a dielectric material to form at least a deep trench isolation structure that extends under the doped well region and contacts the shallow trench isolation structure, the deep trench isolation structure and the shallow trench isolation structure together enclosing the doped well region.