Integrated Circuitry, Memory Arrays Comprising Strings Of Memory Cells, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A method used in forming a memory array comprising strings of memory cells, comprising:

• forming a stack comprising vertically-alternating first tiers and second tiers, the stack comprising a memory-array region and a stair-step region;
• forming a cavity comprising a stair-step structure into the stack in the stair-step region;
• lining sidewalls of the cavity and steps of the stair-step structure with an insulator material;
• forming insulative material in the cavity radially inward of the insulator material;
• removing an upper portion of the insulative material from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure;
• after the removing, forming insulating material in the cavity above the insulative material;
• forming channel-material strings of memory cells through the first and second tiers in the memory-array region;
• and
• forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions extending from the memory-array region into the stair-step region.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a cavity comprising a stair-step structure laterally-adjacent the 3D array;
• and
• insulating material in the cavity above the stair-step structure, the insulating material comprising:
• a radially-inner insulative material;
• and
• a radially-outer insulator material radially outside of the radially-inner insulative material, the radially-inner insulative material and the radially-outer insulator material being of different compositions relative one another.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a cavity comprising a stair-step structure laterally-adjacent the 3D array;
• and
• insulating material in the cavity above the stair-step structure, the insulating material comprising a seam extending laterally across the cavity in a vertical cross-section, the insulating material that is immediately-directly above and the insulating material that is immediately-directly below the laterally-extending seam being of the same composition relative one another.

Integrated circuitry comprising:

• a three-dimensional (3D) array comprising tiers of electronic components;
• a cavity comprising a stair-step structure laterally-adjacent the 3D array;
• and
• insulating material in the cavity above the stair-step structure, the insulating material comprising a pair of opposing lateral projections in the cavity in a vertical cross-section, the opposing lateral projections individually being at least partially characterized by a seam in the vertical cross-section, the insulating material that is immediately-directly-laterally-adjacent both sides of the seam in the vertical cross-section being of the same composition relative one another.