Semiconductor packages and methods of manufacturing the semiconductor packages

A semiconductor package, comprising:

• a first semiconductor chip including a first substrate and a front insulation layer on a front surface of the first substrate;
• a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a second substrate, a second front insulation layer on a front surface of the second substrate, and a second backside insulation layer on a backside surface of the second substrate;
• a third semiconductor chip stacked on the second semiconductor chip, the third semiconductor chip including a third substrate, a third front insulation layer on a front surface of the third substrate, and a through electrode penetrating through the third substrate;
• and
• a fourth semiconductor chip stacked on the third semiconductor chip, the fourth semiconductor chip including a fourth substrate and a fourth front insulation layer on a front surface of the fourth substrate,
• wherein the front surface or the backside surface of the second substrate is arranged to face the front surface of the first substrate,
• wherein the front surface of the fourth substrate is arranged to face the front surface of the third substrate, and
• wherein a backside of the third substrate is arranged to face the backside surface of the second substrate such that the third substrate and the second backside insulation layer are bonded directly to each other, or the backside of the third substrate is arranged to face the front surface of the second substrate such that the third substrate and the second front insulation layer are bonded directly to each other.

A semiconductor package, comprising:

• a package substrate;
• first to fourth semiconductor chips sequentially stacked on the package substrate;
• and
• a molding member on the package substrate to cover the first to fourth semiconductor chips,
• wherein a front surface or a backside surface of a second substrate of the second semiconductor chip is arranged to face a front surface of a first substrate of the first semiconductor chip,
• wherein a front surface of a fourth substrate of the fourth semiconductor chip is arranged to face a front surface of a third substrate of the third semiconductor chip,
• wherein a backside of the third substrate is arranged to face the backside surface of the second substrate such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or wherein the backside of the third substrate is arranged to face the front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other,
• wherein a thickness of the third semiconductor chip is within a range of 5 μm to 20 μm, and a thickness of the second semiconductor chip is within a range of 10 μm to 30 μm, and
• wherein the thickness of the third semiconductor chip is less than or equal to the thickness of the second semiconductor chip.