Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsNAMHOON KIM, CHAJEA JO, Ohguk KWON, HYOEUN KIM, SEUNGHOON YEON
Life of this patent
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Abstract
A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
Claims20
A semiconductor package comprising:
- a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern;
- a second semiconductor chip on a top surface of the first semiconductor chip;
- and
- a bump structure disposed between the first semiconductor chip and the second semiconductor chip,
- wherein the bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.
A semiconductor package comprising:
- a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern disposed on a top surface of the semiconductor substrate, the redistribution pattern having a hole;
- a second semiconductor chip on a top surface of the first semiconductor chip;
- a solder pattern provided in the hole so as to be in contact with an inner sidewall of the redistribution pattern;
- and
- a pillar pattern disposed between the solder pattern and the second semiconductor chip.
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip mounted on the package substrate;
- a second semiconductor chip disposed on a top surface of the first semiconductor chip;
- and
- a bump structure disposed between the first semiconductor chip and the second semiconductor chip,
- wherein the first semiconductor chip comprises:
- a first semiconductor substrate;
- a first circuit layer disposed on a bottom surface of the first semiconductor substrate and comprising first integrated circuits;
- a first through-structure disposed in the first semiconductor substrate;
- a first redistribution pattern disposed on a top surface of the first semiconductor substrate and connected to the first through-structure;
- a first protective layer on a top surface of the first redistribution pattern;
- and
- an upper insulating layer between the first semiconductor substrate and the first redistribution pattern,
- wherein the second semiconductor chip comprises:
- a second semiconductor substrate;
- a second circuit layer disposed on a bottom surface of the second semiconductor substrate and comprising second integrated circuits;
- and
- a chip pad disposed on a bottom surface of the second circuit layer and electrically connected to the second integrated circuits,
- wherein the first redistribution pattern has a hole exposing an inner sidewall of the first redistribution pattern, and
- wherein the bump structure comprises:
- a solder pattern provided in the hole so as to be in contact with the inner sidewall of the first redistribution pattern;
- and
- a pillar pattern between the solder pattern and the chip pad of the second semiconductor chip.
Dependencies are inferred from the claim text.