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US 2022/0013487 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorYOUNG LYONG KIM
Life of this patent
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Abstract
Disclosed is a semiconductor package comprising a package substrate, a substrate on the package substrate, a first semiconductor chip mounted on the substrate, and a stiffener structure on the package substrate and having a hole. The stiffener structure is laterally spaced apart from the substrate. The hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure. When viewed in plan, the hole overlaps a corner region of the package substrate.
Claims20
A semiconductor package, comprising:
- a package substrate;
- a substrate on the package substrate;
- a first semiconductor chip mounted on the substrate;
- and
- a stiffener structure on the package substrate, the stiffener structure having a hole,
- wherein the stiffener structure is laterally spaced apart from the substrate,
- wherein the hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure, and
- wherein, when viewed in plan, the hole overlaps a corner region of the package substrate.
5 more elements
A semiconductor package, comprising:
- a package substrate having a first region and a second region that surrounds the first region, when viewed in plan;
- a first semiconductor chip on the first region of the package substrate;
- a stiffener structure on the second region of the package substrate, the stiffener structure having a hole;
- and
- an adhesive layer between the package substrate and the stiffener structure,
- wherein the hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure, and
- wherein the adhesive layer extends into the hole of the stiffener structure.
4 more elements
A semiconductor package, comprising:
- a package substrate that has a central region, a first edge region, and a second edge region;
- an interposer substrate on a top surface of the central region of the package substrate;
- a plurality of interposer bumps between the package substrate and the interposer substrate;
- an under-fill layer in a gap between the package substrate and the interposer substrate, the under-fill layer encapsulating the interposer bumps;
- a first semiconductor chip mounted on a top surface of the interposer substrate;
- a plurality of first bumps between the interposer substrate and the first semiconductor chip;
- a chip stack mounted on the top surface of the interposer substrate and spaced apart from the first semiconductor chip, the chip stack including a plurality of stacked second semiconductor chips;
- a plurality of second bumps between the second semiconductor chips;
- a stiffener structure on the top surface of the first and second edge regions of the package substrate, the stiffener structure having a hole;
- and
- an adhesive layer between the package substrate and a bottom surface of the stiffener structure,
- wherein the hole penetrates a top surface of the stiffener structure and the bottom surface of the stiffener structure, the hole being on the first edge region of the package substrate, and
- wherein the first edge region of the package substrate is adjacent to a corner where two neighboring side surfaces of the package substrate meet each other.
10 more elements
Dependencies are inferred from the claim text.