# US 2022/0013477 A1 · Semiconductor device and manufacturing method thereof

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- Number: US 2022/0013477 A1
- Document ID: US20220013477A1
- Status: Published application
- Kind: A1
- Application number: 17/189,718
- Filed: 2021-03-02
- Published: 2022-01-13
- Earliest claimed: 2020-07-07
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Soichi HOMMA; Tatsuo MIGITA; Masayuki MIURA; Takeori MAEDA; Kazuhiro KATO; Susumu YAMAMOTO
- Web page: https://patentgrep.com/patent/US20220013477A1

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 74/01: Manufacture or treatment
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/656: Fan-in layouts
- H10W 70/66: Conductive materials thereof
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements on the first face;
columnar electrodes provided above the first face, and electrically connected to any of the semiconductor elements;
a first member located around the columnar electrodes above the first face; and
an insulant covering the columnar electrodes and the first member, wherein
the first member is harder than the columnar electrodes and the insulant, and
the first member and the columnar electrodes are exposed from a surface of the insulant.

### Claim 2 (depends on 1)

The device of claim 1, wherein
the first member comprises a third face exposed from the insulant, a fourth face corresponding to the first face of the semiconductor chip, and a side surface between the third face and the fourth face, and
the side surface is inclined from a perpendicular direction with respect to the first face or has a stepped portion.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first member is a stacked body configured by stacking a plurality of second members having surface areas different from each other as viewed from the first face.

### Claim 4 (depends on 1)

The device of claim 1, wherein any of silicon, glass, alumina, SiC, AlN, ceramics, and a metal is used as the first member.

### Claim 5 (depends on 1)

The device of claim 1, further comprising metallic bumps respectively provided on the columnar electrodes.

### Claim 6 (depends on 1)

The device of claim 1, further comprising an interconnection layer located on the columnar electrodes.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a metallic film between electrode pads of the semiconductor chip and the columnar electrodes, wherein
an area of each of the columnar electrodes exposed from the insulant is larger than a contact area of the columnar electrode to an associated one of the electrode pads of the semiconductor chip.

### Claim 8 (depends on 1)

The device of claim 1, wherein an area of each of the columnar electrodes exposed from the insulant is smaller than a contact area of the columnar electrode to the semiconductor chip.

### Claim 9 (depends on 1)

The device of claim 1, wherein the columnar electrodes include a first columnar electrode in which an area exposed from the insulant is larger than a contact area of the columnar electrode to the semiconductor chip, and a second columnar electrode in which an area exposed from the insulant is smaller than a contact area of the columnar electrode to the semiconductor chip.

### Claim 10 (depends on 5)

The device of claim 5, wherein the first member is a conductive body and is electrically connected to any of the semiconductor elements.

### Claim 11 (depends on 1)

The device of claim 1, wherein
the insulant embeds a plurality of the semiconductor chips stacked, and
the first member is placed on any of the semiconductor chips.

### Claim 12 (depends on 11)

The device of claim 11, wherein
the semiconductor chips are a plurality of memory chips and a controller chip for the memory chips, and
the first member and the controller chip are located on a stacked body of the memory chips.

### Claim 13 (depends on 1)

The device of claim 1, wherein any of a simple substance of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, or the like, a composite membrane including two or more thereof, and an alloy including two or more thereof is used as the columnar electrodes.

### Claim 14 (depends on 1)

The device of claim 1, further comprising a support part provided on the second face of the semiconductor elements.

### Claim 15 (depends on 1)

The device of claim 1, further comprising an interconnection layer on the first face of the semiconductor chip, wherein
the columnar electrodes and the first member are provided in the interconnection layer.

### Claim 16 (depends on 1)

The device of claim 1, further comprising:
a fourth insulating film covering the semiconductor chip; and
an interconnection layer provided on the first face of the semiconductor chip and on a face of the fourth insulating film flush with the first face, wherein
the columnar electrodes and the first member are provided in the interconnection layer.

### Claim 17

A manufacturing method of a semiconductor device, the method comprising:
forming columnar electrodes above a first face of a semiconductor chip, the semiconductor chip having the first face and a second face on an opposite side to the first face and including semiconductor elements on the first face;
providing a first member having an upper surface at a lower location than the columnar electrodes above the first face of the semiconductor chip;
forming an insulant embedding the columnar electrodes and the first member on the first face; and
polishing the insulant and the columnar electrodes until the first member harder than the columnar electrodes and the insulant is exposed.

### Claim 18 (depends on 17)

The method of claim 17, wherein
the first member comprises a third face exposed from the insulant, a fourth face corresponding to the first face of the semiconductor chip, and a side surface between the third face and the fourth face,
the side surface is inclined from a perpendicular direction with respect to the first face or has a stepped portion, and
polishing of the insulant and the columnar electrodes is stopped according to changes in a polishing area of the first member.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first member is formed by stacking a plurality of second members having surface areas different from each other.

### Claim 20 (depends on 17)

The method of claim 17, further comprising forming metallic bumps on the columnar electrodes, respectively.

### Claim 21 (depends on 17)

The method of claim 17, further comprising forming an interconnection layer on the columnar electrodes, respectively.

### Claim 22 (depends on 17)

The method of claim 17, wherein
a metallic film is formed on electrode pads of the semiconductor chip, and
the columnar electrodes are formed on the metallic film by a plating method.

### Claim 23 (depends on 17)

The method of claim 17, wherein the columnar electrodes are respectively formed by bonding metallic wires onto associated electrode pads of the semiconductor chip, and drawing out the metallic wires in a substantially perpendicular direction to the first face.

### Claim 24 (depends on 17)

The method of claim 17, further comprising
stacking a plurality of the semiconductor chips, wherein
the columnar electrodes are respectively formed on the first faces of the semiconductor chips,
the first member is placed on any of the semiconductor chips, and
the insulant embeds a stacked body of the semiconductor chips, the columnar electrodes, and the first member.

### Claim 25 (depends on 24)

The method of claim 24, wherein
the semiconductor chips are a plurality of memory chips and a controller chip for the memory chips, and
the first member and the controller chip are located on a stacked body of the memory chips.