Semiconductor package including underfill and method for manufacturing the same

A semiconductor package comprising:

• at least one logic chip;
• a plurality of memory stacks;
• a molding material surrounding side surfaces of the at least one logic chip and the plurality of memory stacks,
• the molding material including a reference area and at least one recess area,
• the reference area includes a portion having a maximum height, and
• a height of the at least one recess area being lower than the maximum height of the portion of the reference area,
• the molding material, when viewed in a plane, including a plurality of sides and a plurality of edges,
• each of the plurality of edges being defined by two adjacent ones of the plurality of sides, and
• the at least one recess area including the plurality of edges;
• and
• an underfill surrounding a periphery of the molding material while overlapping a portion of the molding material.

A semiconductor package comprising;

• a substrate;
• an interposer on the substrate;
• an underfill between the substrate and the interposer;
• a logic chip on the interposer;
• a first memory stack and a second memory stack on the interposer,
• the first memory stack and the second memory stack being disposed symmetrically with respect to the logic chip while being disposed in parallel;
• and
• a molding material on the interposer while surrounding side surfaces of the logic chip, the first memory stack, and the second memory stack,
• the molding material including a reference area, a first recess area, and a second recess area,
• the first recess area and the second recess area having heights lower than a height of the reference area, and
• the underfill overlapping the first recess area and the second recess area on a side surface of the molding material and on the first recess area and the second recess area, and
• a height of the underfill being higher than the height of the first recess area and lower than the height of the reference area.