Back to results
US 2022/0013465 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsMyungsam Kang, Youngchan Ko, Jeongseok Kim, Bongju Cho
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.
Claims20
A semiconductor package comprising:
- a first redistribution structure having a first surface comprising a first pad and a second pad therein, and a second surface opposite the first surface and comprising a first redistribution layer electrically connected to the first pad and the second pad;
- a vertical connection structure comprising a land layer on the first pad, and a pillar layer on the land layer and electrically connected to the first redistribution layer;
- a semiconductor chip on the first surface of the first redistribution structure and comprising a connection electrode electrically connected to the second pad;
- a first encapsulant on at least a portion of the vertical connection structure and comprising a cavity sized to accept the semiconductor chip;
- a second encapsulant on the first encapsulant and in the cavity;
- and
- a first connection bump on the second surface of the first redistribution structure and electrically connected to the first redistribution layer,
- wherein the land layer is in the first surface of the first redistribution structure, and
- a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer thereon.
6 more elements
A semiconductor package comprising:
- a redistribution structure comprising an insulating layer, a redistribution layer on the insulating layer, and first and second pads in a surface of the insulating layer that is opposite the redistribution layer, wherein the first and second pads are electrically connected to the redistribution layer;
- a semiconductor chip on the redistribution structure and including a connection electrode electrically connected to the second pad;
- a vertical connection structure on the redistribution structure, adjacent the semiconductor chip, and electrically connected to the first pad;
- and
- an encapsulant on the semiconductor chip and the vertical connection structure,
- wherein the vertical connection structure comprises a land layer in the insulating layer and contacting the first pad, and a pillar layer on the land layer, and
- wherein a width of the pillar layer increases in a direction toward the land layer.
4 more elements
A semiconductor package comprising:
- a first redistribution structure comprising a plurality of pads in an upper surface of the first redistribution structure and a first redistribution layer electrically connected to the plurality of pads;
- a vertical connection structure on the upper surface of the first redistribution structure and electrically connected to the first redistribution layer;
- a core structure on the upper surface of the first redistribution structure and electrically connected to the first redistribution layer;
- a semiconductor chip on the upper surface of the first redistribution structure and including connection electrodes;
- an encapsulant on at least a portion of the vertical connection structure, at least a portion of the core structure, and at least a portion of the semiconductor chip;
- and
- a second redistribution structure on the encapsulant and comprising a second redistribution layer electrically connected to the vertical connection structure,
- wherein the plurality of pads include first pads that are electrically connected to the vertical connection structure, second pads that are electrically connected to the core structure, and third pads that are electrically connected to the connection electrodes of the semiconductor chip,
- wherein the vertical connection structure and the core structure comprise first pillar layers and second pillar layers on the first pads and the second pads, respectively, wherein the first and second pillar layers are separated by the encapsulant, and first and second land layers between the first and second pillar layers and the first and second pads, respectively,
- wherein upper surfaces of the third pads have a step difference from the upper surface of the first redistribution structure, respectively, and
- wherein respective thicknesses of the first and second land layers are substantially equal to a height of the step difference.
8 more elements
Dependencies are inferred from the claim text.