Packaged semiconductor assemblies and methods for manufacturing such assemblies
AssigneeMicron Technology, Inc.
InventorsSuan Jeung Boon, Meow Koon Eng, Yong Poo Chia
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Abstract
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.
Claims20
A stacked semiconductor assembly, comprising:
- a first semiconductor package having a first die and a first redistribution structure attached to the first die, wherein the first semiconductor package has a first footprint, and wherein the first redistribution structure includes a first bond site at a periphery of the first semiconductor package having a first inner edge;
- a second semiconductor package carried by the first semiconductor package, the second semiconductor package having a second die generally identical to the first die and a second redistribution structure attached to the second die, wherein the second package has a second footprint smaller than the first footprint, and wherein the second redistribution structure includes a second bond site at a periphery of the second semiconductor package having a second inner edge aligned with the first inner edge along an axis normal to a surface of the first bond site;
- an interconnect structure electrically connecting the first and second redistribution structures;
- and
- an encapsulant disposed at least partially around the interconnect structure and the first and second bond sites.
A stacked semiconductor assembly, comprising:
- a first package including a first die having a first peripheral edge and a first bond site at a periphery of the first package, wherein the first package has a first footprint;
- a second package carried by the first package, the second package including a second die generally identical in size to the first die and a second bond site at a periphery of the second package, wherein the second package has a second footprint smaller than the first footprint, and wherein the second die has a second peripheral edge aligned with the first peripheral edge along an axis generally transverse to the first and second dies;
- an interconnect structure electrically connecting the first and second bond sites;
- and
- an encapsulant disposed at least partially around the interconnect structure and the first and second bond sites.
A stacked semiconductor assembly, comprising:
- a first package, the first package including a first die and a first bond site adjacent a peripheral edge of the first package;
- a second package carried by the first package, the second package including a second die generally identical the first die and a second bond site adjacent a peripheral edge of the second package, and wherein the second bond site at least partially overlaps with the first bond site;
- and
- an interconnect structure electrically coupling the first bond site and the second bond site.
Dependencies are inferred from the claim text.