Compact transistor utilizing shield structure arrangement

A method of forming a transistor comprising:

• forming, on an upper surface of a semiconductor substrate having a first terminal and a second terminal, an interconnect structure from multiple layers of dielectric material and electrically conductive material by:
• forming a first conductive layer of the electrically conductive material,
• forming a second conductive layer of the electrically conductive material spaced apart from the first conductive layer by a first dielectric layer of the dielectric material;
• forming a third conductive layer of the electrically conductive material spaced apart from the second conductive layer by a second dielectric layer of dielectric material;
• and
• configuring the electrically conductive material to form, as parts of the interconnect structure:
• a pillar in electrical contact with the first terminal;
• a first runner formed in the third conductive layer and electrically connected to the pillar;
• a first tap interconnect in electrical contact with the second terminal, the first tap interconnect being formed at a first tap location;
• a second runner formed in the second conductive layer and electrically connected to the first tap interconnect;
• a shield structure formed in the second conductive layer and positioned between the pillar and the first tap interconnect, a segment of the shield structure overlying a portion of the second terminal at the first tap location in a direction perpendicular to the upper surface of the semiconductor substrate;
• and
• a shield runner formed in the third conductive layer and electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate;
• wherein the first, second, and third conductive layers are arranged such that the first conductive layer resides closest to the upper surface of the semiconductor substrate relative to the second and third conductive layers, and the second conductive layer is interposed between the first and third conductive layers.

A method of forming a transistor comprising:

• forming, on an upper surface of a semiconductor substrate having a first terminal and a second terminal, an interconnect structure formed of multiple layers of dielectric material and electrically conductive material by:
• forming a first conductive layer of the electrically conductive material;
• forming a second conductive layer of the electrically conductive material spaced apart from the first conductive layer by a first dielectric layer of the dielectric material;
• forming a third conductive layer electrically conductive material spaced apart from the second conductive layer by a second dielectric layer of dielectric material, wherein the first conductive layer resides closest to the upper surface of the semiconductor substrate relative to the second and third conductive layers, and the second conductive layer is interposed between the first and third conductive layers;
• and
• configuring the electrically conductive material to form, as parts of the interconnect structure:
• a pillar in electrical contact with the first terminal;
• a first runner formed in the third conductive layer and electrically connected to the pillar;
• a tap interconnect in electrical contact with the second terminal, the tap interconnect including a first tap interconnect segment formed in the second conductive layer;
• a second runner in the second conductive layer and electrically connected to the tap interconnect;
• a shield structure in the second conductive layer and positioned between the pillar and the tap interconnect, the shield structure including a base segment, a first leg, and a second leg, the first and second legs extending from opposing ends of the base segment in a direction that is antiparallel to a length of the base segment, wherein the first tap interconnect segment of the tap interconnect resides between the first and second legs;
• and
• a shield runner in the third conductive layer and electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.