Integrated chip with cavity structure

A method of forming an integrated chip, the method comprising:

• forming a first metal feature and a second metal feature over a substrate;
• forming a first dielectric liner segment between the first metal feature and the second metal feature and along sidewalls of the first metal feature and the second metal feature;
• forming a sacrificial segment between the sidewalls of the first metal feature and the second metal feature, and further between sidewalls of the first dielectric liner segment;
• forming an etch-stop layer over the first metal feature, over the second metal feature, over the sacrificial segment, and over the first dielectric liner segment;
• and
• removing at least part of the sacrificial segment from between the sidewalls of the first metal feature and the second metal feature and from between the sidewalls of the first dielectric liner segment, thereby leaving a first cavity in place where the at least part of the sacrificial segment has been removed.

A method for forming an integrated chip, the method comprising:

• forming an interlayer dielectric (ILD) layer over a substrate;
• forming a first sacrificial layer over the ILD layer;
• patterning the first sacrificial layer to define a first sacrificial segment over the ILD layer;
• patterning the ILD layer to form an opening in the ILD layer;
• depositing a metal over the substrate to form a first metal feature and a second metal feature on opposite sides of the first sacrificial segment, wherein the first metal feature extends from a top surface of the first sacrificial segment to a bottom surface of the first sacrificial segment, and wherein the second metal feature extends from the top surface of the first sacrificial segment to below a bottom surface of the ILD layer;
• removing, at least in part, the first sacrificial segment from between the first metal feature and the second metal feature;
• forming a first dielectric liner segment on a sidewall of the first metal feature that faces the second metal feature, on a sidewall of the second metal feature that faces the first metal feature, and between the first metal feature and the second metal feature on an upper surface of the ILD layer;
• forming a second sacrificial segment over an upper surface of the first dielectric liner segment and between sidewalls of the first dielectric liner segment;
• forming an etch-stop layer over a top surface of the second sacrificial segment, over a top surface of the first metal feature, over a top surface of the second metal feature, and over a top surface of the first dielectric liner segment;
• and
• removing, at least in part, the second sacrificial segment from over the upper surface of the first dielectric liner segment, thereby leaving a first cavity in its place, wherein the first cavity is defined by the sidewalls of the first dielectric liner segment, the upper surface of the first dielectric liner segment, and a lower surface of the etch-stop layer.

A method for forming an integrated chip, the method comprising:

• depositing a first sacrificial layer over a dielectric layer that is over a substrate;
• patterning the first sacrificial layer to form a first sacrificial segment, a second sacrificial segment, and a third sacrificial segment from the first sacrificial layer that are laterally spaced apart over the dielectric layer, wherein the second sacrificial segment is laterally between the first sacrificial segment and the third sacrificial segment;
• depositing a metal between the first sacrificial segment and the second sacrificial segment to form a first metal feature between the first sacrificial segment and the second sacrificial segment;
• depositing the metal between the second sacrificial segment and the third sacrificial segment to form a second metal feature between the second sacrificial segment and the third sacrificial segment;
• removing, at least in part, the second sacrificial segment from between the first metal feature and the second metal feature;
• depositing a dielectric liner layer along a sidewall of the first metal feature that faces the second metal feature, along a sidewall of the second metal feature that faces the first metal feature, and between the first metal feature and the second metal feature along an upper surface of the dielectric layer;
• depositing a second sacrificial layer over a first upper surface of the dielectric liner layer and between opposing sidewalls of the dielectric liner layer;
• removing a portion of the second sacrificial layer and a portion of the dielectric liner layer to form a fourth sacrificial segment and a dielectric liner segment from the second sacrificial layer and the dielectric liner layer, respectively, the fourth sacrificial segment and the dielectric liner segment arranged between the first metal feature and the second metal feature;
• depositing an etch-stop layer over a top surface of the fourth sacrificial segment, over a top surface of the first metal feature, over a top surface of the second metal feature, and over a second upper surface of the dielectric liner segment;
• and
• removing, at least in part, the fourth sacrificial segment from over the first upper surface of the dielectric liner segment, from between the opposing sidewalls of the dielectric liner segment, and from below a lower surface of the etch-stop layer, thereby leaving a first cavity in place of the second sacrificial layer.