Adaptive memory management and control circuitry
AssigneeNumem Inc.
InventorsEric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Abstract
An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.
Claims20
Resistive memory comprising:
- a resistive memory array;
- and
- an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test, reliability, performance or power optimizing capabilities.
A memory subsystem comprising:
- a smart compute memory circuitry;
- a resistive memory array coupled to the smart compute memory circuitry;
- and
- an Adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test and performance optimizing capabilities.
A computer-implemented method for providing adaptive memory management and control to
- a resistive memory, the computer-implemented method comprising:
- mapping adaptive memory management and control features to a memory mapped region of the resistive memory of a memory subsystem;
- loading a custom test code into a first memory region of the resistive memory;
- and
- executing, with a smart compute memory circuitry of the memory subsystem, the custom test code to test a second memory region of the resistive memory.
Dependencies are inferred from the claim text.