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US 2022/0013167 A1Published application
Reading a multi-level memory cell
AssigneeMicron Technology, Inc.
InventorsMattia Robustelli, Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano
Life of this patent
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Abstract
Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
Claims24
A method, comprising:
- applying a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determining whether a first snapback event occurred after applying the first read voltage;
- applying a second read voltage with a second polarity different than the first polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determining whether a second snapback event occurred after applying the second read voltage;
- and
- determining the logic state stored by the memory cell from the three or more logic states based at least in part on determining whether the first snapback event or the second snapback event occurred.
3 more elements
A method, comprising:
- applying a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determining whether a first snapback event occurred after applying the first read voltage;
- applying a second read voltage with a second polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determining whether a second snapback event occurred after applying the second read voltage;
- applying a third read voltage with the first polarity and a magnitude greater than a magnitude of the second read voltage to the memory cell based at least in part on determining that the second snapback event failed to occur;
- determining whether a third snapback event occurred after applying the third read voltage;
- determining the logic state stored by the memory cell based at least in part on determining whether the first snapback event, the second snapback event, or the third snapback event occurred;
- determining that the third snapback event occurred;
- and
- performing a reprogram operation on the memory cell after determining the logic state stored by the memory cell based at least in part on determining that the third snapback event occurred.
7 more elements
A method, comprising:
- applying a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determining whether a first snapback event occurred after applying the first read voltage;
- applying a second read voltage with a second polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determining whether a second snapback event occurred after applying the second read voltage;
- applying a third read voltage with the second polarity and a magnitude greater than a magnitude of the second read voltage to the memory cell based at least in part on determining that the second snapback event failed to occur;
- determining whether a third snapback event occurred after applying the third read voltage;
- determining the logic state stored by the memory cell based at least in part on determining whether the first snapback event, the second snapback event, or the third snapback event occurred;
- determining that the third snapback event occurred;
- and
- performing a reprogram operation on the memory cell after determining the logic state stored by the memory cell based at least in part on determining that the third snapback event occurred.
7 more elements
15-24. (canceled)
An apparatus comprising:
- a memory array comprising a memory cell;
- and
- a control component coupled with the memory array, the control component configured to cause the apparatus to:
- apply a first read voltage with a first polarity to the memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determine whether a first snapback event occurred after applying the first read voltage;
- apply a second read voltage with a second polarity different than the first polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determine whether a second snapback event occurred after applying the second read voltage;
- and
- determine the logic state stored by the memory cell from the three or more logic states based at least in part on determining whether the first snapback event or the second snapback event occurred.
6 more elements
An apparatus comprising:
- a memory array comprising a memory cell;
- and
- a control component coupled with the memory array, the control component configured to cause the apparatus to:
- apply a first read voltage with a first polarity to the memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determine whether a first snapback event occurred after applying the first read voltage;
- apply a second read voltage with a second polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determine whether a second snapback event occurred after applying the second read voltage;
- apply a third read voltage with the first polarity and a magnitude greater than a magnitude of the second read voltage to the memory cell based at least in part on determining that the second snapback event failed to occur;
- determine whether a third snapback event occurred after applying the third read voltage;
- determining the logic state stored by the memory cell based at least in part on determining whether the first snapback event, the second snapback event, or the third snapback event occurred;
- determine that the third snapback event occurred;
- and
- perform a reprogram operation on the memory cell after determining the logic state stored by the memory cell based at least in part on determining that the third snapback event occurred.
10 more elements
29-32. (canceled)
A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
- apply a first read voltage with a first polarity to a memory cell to determine a logic state stored by the memory cell configured to store three or more logic states;
- determine whether a first snapback event occurred after applying the first read voltage;
- apply a second read voltage with a second polarity different than the first polarity to the memory cell based at least in part on determining that the first snapback event failed to occur;
- determine whether a second snapback event occurred after applying the second read voltage;
- and
- determine the logic state stored by the memory cell from the three or more logic states based at least in part on determining whether the second snapback event occurred.
3 more elements
Dependencies are inferred from the claim text.