Memory device and operation method thereof

A memory device, comprising:

• an input/output data latch circuit, coupled between a main input/output line pair and a local input/output line pair;
• and
• a bit line sensing amplifier circuit, wherein the local input/output line pair is coupled to a plurality of bit line pairs through the bit line sensing amplifier circuit,
• wherein the memory device performs a two-stage operation to input or output data of a selected bit line pair among the bit line pairs when the memory device performs a read operation or a write operation,
• wherein the selected bit line pair connects to the local input/output line pair only during one stage operation of the two-stage operation, and the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair during the other stage operation of the two-stage operation,
• wherein the bit line sensing amplifier circuit comprises a plurality of sensing amplification data latches, configured to store data of the bit line pairs,
• wherein the two-stage operation comprises a first-stage operation and a second-stage operation,
• wherein when the memory device performs the read operation, the data of the selected bit line pair is latched to the input/output data latch circuit from the corresponding sensing amplification data latch during the first-stage operation, and the data latched in the input/output data latch circuit is transmitted to the main input/output line pair during the second-stage operation,
• wherein when the memory device performs the write operation, write data is latched to the input/output data latch circuit from the main input/output line pair during the first-stage operation, and the write data latched in the input/output data latch circuit is transmitted to the sensing amplification data latch corresponding to the selected bit line pair during the second-stage operation.