US 2022/0012397 A1Published application

Automated assisted circuit validation

AssigneeTektronix, Inc.

InventorDavid Everett Burgess

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Abstract

A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

Claims23

Dependent claims

A method for automated assisting of circuit validation, the method comprising:

categorizing one or more nodes of a fabricated circuit as being a priority node and one or more nodes of the fabricated circuit as being an inferior node, each inferior node being on a same sub-portion of the fabricated circuit as at least one of the priority nodes;
evaluating a first priority node by automatically designating for verification the first priority node from the priority nodes, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node;
evaluating, when the measured signal from the first priority node meets the pass-fail criterion for the first priority node, a second priority node by automatically designating for verification the second priority node from the priority nodes, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node;
and
evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion for the first priority node, a first inferior node, the first inferior node being on the same sub-portion of the fabricated circuit as the first priority node, by automatically designating for verification the first inferior node from the inferior nodes, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

2 more elements

A non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by a computing device, cause the computing device to perform operations, the operations comprising:

evaluating a first priority node by automatically designating for verification the first priority node from a group of priority nodes, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node;
evaluating, when the measured signal from the first priority node meets the pass-fail criterion for the first priority node, a second priority node by automatically designating for verification the second priority node from the group of priority nodes, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node;
and
evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion for the first priority node, a first inferior node, the first inferior node being on the same sub-portion of the fabricated circuit as the first priority node, by automatically designating for verification the first inferior node from a group of inferior nodes, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/370,976Filed 8 Jul 2021
Priority: 9 Jul 2020
Published: 13 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
G01R 31/31835
By preliminary fault modelling, e.g. analysis, simulation: analysis of test coverage or failure detectability
G01R 31/318357
By preliminary fault modelling, e.g. analysis, simulation: simulation
G06F 30/323
Circuit design at the digital level: translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist…