Digital signal processing circuit and corresponding method of operation

A circuit comprising:

• a plurality of processing units comprising a number P of processing units,
• a plurality of data memory banks configured to store data;
• and
• a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform (FFT) processing, the plurality of coefficient memory banks comprising a number P of coefficient memory banks equal to the number P of processing units;
• wherein the circuit is configured to apply the FFT processing having a size N, in a form N=2n with n being an integer, to the data stored in the data memory banks, and wherein applying the FFT processing having the size N comprises processing the data in a plurality of FFT computation stages comprising a number n of FFT computation stages, wherein each FFT computation stage comprises a number of FFT computation cycles;
• wherein the processing units are configured to:
• fetch at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction;
• fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks;
• process the input data and the set of twiddle factors to generate output data;
• and
• store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.