Semiconductor device
AssigneeFujitsu Limited
InventorHiroyuki Ishii
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a core which includes a first cache and a second cache; and a third cache configured to connect to the core, wherein the core is configured to: hold a read instruction that is issued from the first cache to the second cache, hold a write-back instruction that is issued from the first cache to the second cache, process the read instruction and the write-back instruction, determine whether a target address of the read instruction is held by the first cache by using a cache tag that indicates a state of the first cache, and when data of the target address is held by the first cache, abort the read instruction until it is determined that data of the target address is not held by the first cache.
Claims8
A semiconductor device comprising:
- a core which includes a first cache and a second cache;
- and
- a third cache configured to connect to the core, wherein
- the core is configured to:
- hold a read instruction that is issued from the first cache to the second cache,
- hold a write-back instruction that is issued from the first cache to the second cache,
- process the read instruction and the write-back instruction,
- determine whether a target address of the read instruction is held by the first cache by using a cache tag that indicates a state of the first cache, and
- when data of the target address is held by the first cache, abort the read instruction until it is determined that data of the target address is not held by the first cache.
A semiconductor device comprising:
- a calculation unit that executes an instruction;
- a higher cache connected to the calculation unit;
- and
- a lower cache connected to the higher cache,
- wherein the lower cache includes:
- a first port that holds a read instruction received from the higher cache,
- a second port that holds a write-back instruction received from the higher cache,
- a processing unit that processes the read instruction input from the first port and the write-back instruction input from the second port,
- a cache unit that holds data, and
- a higher cache tag that indicates a state of the higher cache,
- wherein the processing unit aborts the read instruction input from the first port, until the higher cache tag indicates that the higher cache does not hold the data of the target address, when the higher cache tag indicates that the higher cache holds data of a target address of the read instruction input from the first port.
Dependencies are inferred from the claim text.