Cache-based tracing for time travel debugging and analysis

A method, implemented at a processor comprising a plurality of registers including at least one general register and at least one model-specific register, and a processor cache, the method comprising:

• initiating recording a trace of execution of an execution entity, including recording initial processor register state for the execution entity into the trace, the recorded initial processor register state including a value of at least one register of the plurality of registers;
• based on detection of a cache miss during execution of the execution entity subsequent to the recording of the initial processor register state for the execution entity into the trace, recording an influx of data imported into the processor cache in response to the cache miss;
• and
• based on execution of a non-deterministic processor instruction of the execution entity subsequent to the recording of the initial processor register state for the execution entity into the trace, recording at least one side effect of an access to the at least one model-specific register, including recording a change in the value of the at least one register of the plurality of registers, the change resulting from the execution of the non-deterministic processor instruction of the execution entity.