US 2022/0012129 A1Published application

Methods and apparatus to increase resiliency in self-healing mechanisms

AssigneeIntel Corporation

InventorsKshitij Arun Doshi, Francesc Guim Bernat, Christian Maciocco, Satish Jha, Vesh Raj Sharma Banjade, S M Iftekharul Alam, Alexander Bachmutsky

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Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to increase resiliency in self-healing mechanisms. At least one non-transitory machine-readable medium comprises instructions that, when executed, cause at least one processor to at least partition computational resources of a first host into a primary partition and a shadow partition, the primary partition to communicate with a second host, apply a fix for the primary partition, determine if the primary partition can communicate with the second host during the application of the fix, cause, in response to the determination that the primary partition cannot communicate with the second host during the application of the fix, the shadow partition to communicate with the second host; and transfer communication with the second host from the shadow partition to the primary partition, the transfer in response to a determination that the application of the fix is complete.

An apparatus to improve resiliency in self-healing mechanisms comprising:

memory;
and
processor circuitry including one or more of:
at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations;
or
Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate:
partitioner circuitry to partition computational resources of a first host into a primary segment and a secondary segment, the primary segment to communicate with a second host;
fix management circuitry to:
apply a fix for the primary segment;
determine if the primary segment can communicate with the second host during the application of the fix;
cause, in response to the determination that the primary segment cannot communicate with the second host during the application of the fix, the secondary segment to communicate with the second host;
and
transfer communication with the second host from the secondary segment to the primary segment, the transfer in response to a determination that the application of the fix is complete.

12 more elements

Facts

Application

17/484,951Filed 24 Sep 2021

Published

13 Jan 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 11/1423
Reconfiguring to eliminate the error: by reconfiguration of paths
G06F 11/2025
Failover techniques: using centralised failover control functionality
G06F 11/0751
Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of…
G06F 11/0772
Error or fault reporting or storing: means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

Claims28