Asymmetric llr generation using assist-read
AssigneeSK hynix Inc.
InventorsFan Zhang, Aman Bhatia
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AssigneeSK hynix Inc.
InventorsFan Zhang, Aman Bhatia
Estimating the term…
A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.
A method of operating a storage system, the storage system including memory cells and a memory controller coupled to the memory cells for controlling operations of the memory cells, wherein each memory cell is a 3-bit tri-level cell (TLC), wherein the memory cells are arranged in LSB (least significant bit) pages, CSB (center significant bit) pages, and, MSB (most significant bit) pages, wherein each of the memory cells comprises eight programmed voltage (PV) levels (PV0-PV7), wherein PV0 is an erased state, the method comprising:
A method of operating a storage system, the storage system including memory cells and a memory controller coupled to the memory cells for controlling operations of the memory cells, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, the memory cells arranged in m pages, each of the m bits of a given memory cell providing data for a corresponding one of the m pages, the method comprising:
A storage system, the storage system including memory cells and a memory controller coupled to the memory cells for controlling operations of the memory cells, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, the memory cells arranged in m pages, each of the m bits of a given memory cell providing data for a corresponding one of the m pages, wherein the memory controller is configured to:
Dependencies are inferred from the claim text.