Superconducting tunable inductance

A method of fabricating a superconducting integrated circuit, the method comprising:

• depositing a ground plane to at least partially overlie a substrate, the ground plane which is electrically communicatively coupleable to an electrical ground;
• depositing an insulating layer to at least partially overlie the ground plane;
• depositing a superconducting layer to at least partially overlie the insulating layer;
• forming a superconducting feature in the superconducting layer, wherein an inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane, and wherein the depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material, a second critical current density of the second superconducting material which is higher than a first critical current density of the first superconducting material.