Methods and processes for forming electrical circuitries on three-dimensional geometries
AssigneeDujud LLC
InventorReza Abbaspour
Life of this patent
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Abstract
Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes forming selectively shaped 3D structures using additive manufacturing. The method includes forming undercuts on upper-level pedestals of the 3D structures that effectively act as overhanging deposition masks for selectively preventing deposition of a selected material on a corresponding portions of lower levels. The method includes simultaneously forming and electrically isolating materials directionally deposited on the 3D structure.
Claims23
A method of additively manufacturing an electronic device structure, the method comprising:
- forming a 3D structure, the 3D structure characterized by:
- an upper level;
- a lower level;
- and
- a pedestal portion joining the upper level and the lower level, the pedestal portion comprising an undercut, wherein the undercut defines an upper level overhang configured to define a mask region over a portion of the lower level;
- and
- directionally depositing a selected material on at least the upper level and one or more non-masked portions of the lower level, wherein the one or more non-masked portions of the lower level are not masked by the upper level overhang, wherein the upper level overhang is configured to prevent deposition of the selected material on the portion of the lower level that is masked by the upper level overhang.
A three-dimensional (3D) electronic circuit, comprising:
- electrically conductive traces formed by deposition of a selected material on a 3D structure formed by an additive polymer photocuring process, the 3D structure comprising:
- an upper level;
- a lower level;
- and
- a pedestal portion joining the upper level and the lower level, the pedestal portions comprising an undercut;
- wherein the undercut defines an upper level overhang configured to define a mask region on a corresponding portion of the lower level to prevent deposition of the selected material on the corresponding portions of the lower level that are masked by the upper level overhang;
- wherein the electrically conductive traces are selectively isolated from one another by one or more of the mask region and the undercut;
- and
- wherein the undercut is configured to selectively define the mask region directly below the upper level overhang to prevent deposition of the selected material on the corresponding portion of the lower level while allowing deposition of the selected material on upper level regions and on lower level regions that are not masked by the upper level overhang.
Dependencies are inferred from the claim text.