# US 2021/0344956 A1 · Encoder, decoder, encoding method, and decoding method

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- Number: US 2021/0344956 A1
- Document ID: US20210344956A1
- Status: Published application
- Kind: A1
- Application number: 17/373,066
- Filed: 2021-07-12
- Published: 2021-11-04
- Earliest claimed: 2016-05-27
- Assignees: Panasonic Intellectual Property Corporation of America
- Applicants: Panasonic Intellectual Property Corporation of America
- Inventors: Chong Soon LIM; Han Boon TEO; Takahiro NISHI; Tadamasa TOMA; Ru Ling LIAO; Sughosh Pavan SHASHIDHAR; Hai Wei SUN
- Web page: https://patentgrep.com/patent/US20210344956A1

## CPC

- H04N 19/597: specially adapted for multi-view video sequence encoding
- G06T 5/80: Geometric correction
- H04N 19/159: Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
- H04N 19/176: the region being a block, e.g. a macroblock
- H04N 19/46: Embedding additional information in the video signal during the compression process (H04N19/517, H04N19/68, H04N19/70 take precedence)
- H04N 19/85: using pre-processing or post-processing specially adapted for video compression
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

An encoder capable of properly handling an image to be encoded or decoded includes processing circuitry and memory connected to the processing circuitry. Using the memory, the processing circuitry: obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images; generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images; and writes the parameters into a bitstream including the encoded image.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

An encoder, comprising:
processing circuitry; and
memory connected to the processing circuitry,
wherein, using the memory, the processing circuitry:
encodes a plurality of regions in a first picture;
reconstructs the encoded plurality of regions;
generates a second picture by an arrangement process in which the reconstructed plurality of regions are arranged in a way in which an object within neighboring regions among the reconstructed plurality of regions is continuous; and
stores the second picture in the memory as a reference frame for an inter prediction process.

### Claim 22 (depends on 21)

The encoder according to claim 21, wherein the processing circuitry obtains one or more parameters related to the arrangement process.

### Claim 23 (depends on 22)

The encoder according to claim 22, wherein the processing circuitry writes the one or more parameters into supplemental enhancement information (SEI) in a bitstream.

### Claim 24

An encoder, comprising:
processing circuitry; and
memory connected to the processing circuitry,
wherein, using the memory, the processing circuitry:
obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images;
generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images;
writes the parameters into a bitstream including the encoded image; and
stores a stitched reconstructed image into the memory as a reference frame to be used in an inter prediction process, the stitched reconstructed image being generated by stitching the plurality of images in a way in which an object within neighboring images among the plurality of images is continuous.
