# US 2021/0344858 A1 · Pixel circuit for an ultra-low power image sensor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0344858 A1 - Document ID: US20210344858A1 - Status: Published application - Kind: A1 - Application number: 17/258,938 - Filed: 2019-07-09 - Published: 2021-11-04 - Earliest claimed: 2018-07-10 - Assignees: Csem Centre Suisse D'Electronique Et De Microtechnique SA—Recherche Et DéVeloppement - Applicants: CSEM Centre Suisse d'Electronique et de Microtechnique SA - Recherche et Développement - Inventors: Pascal Heim; Pierre-François Rüedi; Riccardo Quaglia; Engin Türetken; Pascal Nussbaum - Web page: https://patentgrep.com/patent/US20210344858A1 ## CPC - H04N 25/709: Circuitry for control of the power supply - H04N 25/57: Control of the dynamic range - H04N 25/771: comprising storage means other than floating diffusion - H04N 25/571: involving a non-linear response - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A pixel circuit for a ultra-low power image sensor, including: an integration node, on which a photodiode current is integrated, a comparator arranged to compare a voltage at the integration node with a reference voltage, a n+1 bits digital memory, a writing pulse signal generator arranged to generate a writing pulse signal, on the basis of the comparator output voltage and on the voltage at a memory node, the start of the pulse triggering the writing of the digital word in the n-bits digital memory part. The comparator includes a switch in series with a current source and arranged to be commanded by the voltage at the memory node so that the switch is open at the end of the pulse, so as to drastically limit the consumption of static power of the pixel circuit during the integration phase. ## Claims ### Claim 1 A pixel circuit for a ultra-low power image sensor, comprising: a photodiode for receiving a light beam representing a visual scene and for generating a photodiode current, an integration node, on which said photodiode current is integrated during an integration phase, a comparator arranged to compare a voltage at said integration node with a reference voltage, and to generate a comparator output voltage, said comparator comprising a current source arranged for generating a current, a memory element comprising a memory node, a writing pulse signal generator arranged to generate a writing pulse signal, on the basis of said comparator output voltage and on the voltage at said memory node, said writing pulse signal comprising a pulse having a start and an end, characterised in that said comparator further comprises a switch in series with said current source, said switch being arranged to be commanded by the voltage at said memory node so that said switch is open at the end of said pulse, so as to limit the consumption of static power of the pixel circuit during said integration phase. ### Claim 2 (depends on 1) The pixel circuit of claim 1, wherein the memory element is a one-bit digital memory element, the pixel circuit further comprising a n-bits digital memory element for storing a digital word representative of the time elapsed since the beginning of the integration phase, where the writing pulse generator triggers the writing of said digital word in said n-bits digital memory element. ### Claim 3 (depends on 1) The pixel circuit of claim 1, said comparator being arranged so that the current in said comparator is null at the beginning of said integration phase and reaches the value of said current at the instant in which the voltage at said integration node reaches the reference voltage, corresponding to the time of generation of the writing pulse signal. ### Claim 4 (depends on 1) The pixel circuit of claim 1, said current source comprising a first transistor of a first type, said comparator comprising also a second transistor of a second type different from the first type, and comprising a first terminal connected to said reference voltage, a second terminal connected to said integration node, said second transistor being in series with the first transistor, said switch being placed between the first transistor and the second transistor. ### Claim 5 (depends on 1) The pixel circuit of claim 1, comprising a cascode transistor between the photodiode and the integration node, so as to raise the sensibility of the pixel circuit. ### Claim 6 (depends on 5) The pixel circuit of claim 5, comprising a clamp transistor connected between the integration node and a supply voltage, so as to prevent a desaturation of the cascode transistor. ### Claim 7 (depends on 1) The pixel circuit of claim 1, comprising a transfer gate and wherein the photodiode is connected to the integration node through said transfer gate. ### Claim 8 (depends on 1) The pixel circuit of claim 1, comprising a reset switch allowing to reset the voltage at the integration node to a local black level voltage during a reset phase preceding said integration phase. ### Claim 9 (depends on 8) The pixel circuit of claim 8, wherein the fourth terminal of the second transistor and the fourth terminal of a transistor of the reset switch are shared so as to raise the voltage range during the integration phase. ### Claim 10 (depends on 1) The pixel circuit of claim 1, comprising an inverter at the output of the comparator, said inverter being arranged so that when the output voltage of the comparator is in a first state or in a second state, there is no static current consumption in the inverter. ### Claim 11 (depends on 10) The pixel circuit of claim 10, said inverter comprising a current source limiting the power consumption of the inverter during the transition from the first state to the second state of the output voltage Vcmp of the comparator. ### Claim 12 (depends on 4) The pixel circuit of claim 4, wherein the photodiode is a pinned photodiode, the pixel circuit comprising also a transfer gate between the pinned photodiode and the gate of said second transistor. ### Claim 13 (depends on 12) The pixel circuit of claim 12, wherein the pixel circuit is operated with the voltage at the transfer gate kept high all the time. ### Claim 14 (depends on 13) The pixel circuit of claim 13, comprising a cascode transistor between the transfer gate and the integration node, to shield the integration node from the parasitic capacitance of the pinned photodiode, and a clamp transistor connected between the integration node and a supply voltage for preventing the integration node to drop below the saturation voltage of the cascode transistor. ### Claim 15 (depends on 12) The pixel circuit of claim 12, the transfer gate being a first transfer gate, the pixel circuit comprising a second transfer gate connected between the photodiode and a high voltage node, to enable to reset the photodiode independently of the time when charges are transferred to the integration node. ### Claim 16 (depends on 1) The pixel circuit of claim 1, comprising a source follower and a capacitor comprising a first terminal and a second terminal, wherein the first terminal is connected to the gate of the second transistor, wherein the second terminal is connected to the output of the source follower, wherein the photodiode is connected to the gate of the source follower as well as to the source of an nmos or a pmos reset transistor used to reset the photodiode at a defined voltage, and wherein the capacitance of the capacitor is chosen to be much larger than the capacitance of the sense node, so as to store the KTC noise of the sense node. ### Claim 17 (depends on 16) The pixel circuit of claim 16, where the photodiode is connected to a first terminal of a cascode transistor and a second terminal of the cascode transistor is connected to the gate of the source follower and the source of the reset transistor. ### Claim 18 (depends on 16) The pixel circuit of claim 16, wherein the source follower is a pmos source follower. ### Claim 19 (depends on 16) The pixel circuit of claim 16, wherein the photodiode is a pinned photodiode, the pixel circuit comprising also a transfer gate between the pinned photodiode and the gate of said second transistor, wherein the gate of the source follower is connected to a first terminal of the transfer gate, the second terminal of the transfer gate being connected to the pinned photodiode. ### Claim 20 (depends on 19) The pixel circuit of claim 19, wherein a cascode transistor is inserted between the transfer gate and the gate of the source follower. ### Claim 21 (depends on 1) A ultra-low power image sensor, comprising: an array of pixels, each pixel being one pixel according to claim 1, an oscillator generating a clock, a counter module for counting the number of periods of the clock having elapsed since the beginning of the integration phase, and for delivering said number as a binary code to the n+1 bits digital memory. ### Claim 22 (depends on 21) The ultra-low power image sensor according to claim 21, wherein said counter module comprises a first counter, the image sensor comprising a second counter, said first counter being clocked by a clock generator so as to generate pulses at exponentially increasing intervals to clock the second counter, the output of the second counter being proportional to the logarithm of the time of the integration phase. ### Claim 23 (depends on 21) A camera device comprising: a optic module, the image sensor according to claim 21, for acquiring the image from the optic module, a memory, a microcontroller. ### Claim 24 (depends on 23) The camera device of claim 23, wherein said microcontroller is configured for computing the difference between an acquired sub-sampled image and a reference sub-sampled image, and if this difference is larger than a given threshold value for any pixel of the sub-sampled image the microcontroller is configured for performing at least one of the following steps: acquiring a full resolution image, compressing those part of the image where said difference is higher than said threshold, storing the result in said camera memory, updating the pixels of said reference frame with the value of the corresponding pixels in said part of the image which were compressed and stored.