# US 2021/0344616 A1 · Use of stashing buffers to improve the efficiency of crossbar switches

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- Number: US 2021/0344616 A1
- Document ID: US20210344616A1
- Status: Published application
- Kind: A1
- Application number: 17/377,943
- Filed: 2021-07-16
- Published: 2021-11-04
- Earliest claimed: 2018-12-04
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corp.
- Inventors: Matthias Augustin Blumrich; Nan Jiang; Larry Robert Dennison
- Web page: https://patentgrep.com/patent/US20210344616A1

## CPC

- H04L 49/101: using crossbar or matrix
- H04L 49/254: {Centralised controller, i.e. arbitration or scheduling}
- H04L 49/3018: {Input queuing}
- H04L 49/3027: {Output queuing}
- H04L 49/3036: {Shared queuing}
- H04L 49/70: {Virtual switches}
- H04L 49/9047: including multiple buffers, e.g. buffer pools
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

## Claims

### Claim at position 1

1-21. (canceled)

### Claim 22

A switch comprising:
a plurality of input ports receiving packets into an input port buffer;
a plurality of output ports receiving packets from an output port buffer;
a stash partition comprising memory addresses allocated from both of the input port buffer and the output port buffer;
a switching fabric interposed between the input port buffer and the output port buffer; and
a packet path from the stash partition through the switching fabric and back to the stash partition, the packet path bypassing the input ports and the output ports.

### Claim 23 (depends on 22)

The switch of claim 22,the packet path comprising a plurality of virtual channels.

### Claim 24 (depends on 22)

The switch of claim 22, the packet recirculating data path comprising a storage virtual channel coupling the stash partition to inputs of the switching fabric.

### Claim 25 (depends on 24)

The switch of claim 24, the packet recirculating data path comprising a retrieval virtual channel coupling outputs of the switching fabric to the stash partition.

### Claim 26 (depends on 22)

The switch of claim 22, further comprising logic to route the packets from the input port buffer to the stash partition based on a join-shortest-queue algorithm.

### Claim 27 (depends on 22)

The switch of claim 22, wherein the stash partition comprises a plurality of dual-ported memory banks.

### Claim 28 (depends on 22)

The switch of claim 22, further comprising logic to manage the stash partition using a heap algorithm.

### Claim 29

A switch comprising:
a first switch fabric coupling a plurality of packet sources to a plurality of packet destinations; and
a second switch fabric also coupling the plurality of packet sources to the plurality of packet destinations; and
a stash partition coupled to the first switch fabric and to the second switch fabric, the stash partition comprising memory addresses from both of input buffers and output buffers of the switch; and
logic to:
store, in the stash partition, packets that pass from the packet sources to the packet destinations through the second switch fabric; and
recirculate the packets through the first switch fabric from the stash partition to the packet destinations.

### Claim 30 (depends on 29)

The switch of claim 29, further comprising a storage virtual channel and a retrieval virtual channel to recirculate the packets through the first switch fabric from the stash partition to the packet destinations.

### Claim 31

A switch comprising:
a plurality of input ports;
a plurality of output ports;
a switching fabric ;
a buffer memory coupled to both of the input ports and the output ports and comprising:
a first memory allocation for a buffer partition, and
a second memory allocation for a stash partition, the stash partition coupled to recirculate packets received at the input ports through the switching fabric while bypassing the input ports and output ports; and
memory management logic configured to control the allocations of the buffer partition and the stash partition.

### Claim 32 (depends on 1)

The switch of claim 1, the stash partition comprising memory addresses from both of an input port buffer and an output port buffer.

### Claim 33

A switch comprising:
a switching fabric to route packets received at input ports of the switch to output ports of the switch;
an input buffer to store the packets received at the input ports prior to routing the packets through the switching fabric;
an output buffer to store packets routed through the switching fabric prior to outputting the packets from the output ports;
a stash partition formed from both of the input buffer and the output buffer; and
wherein the input buffer, the output buffer, and the stash partition form a path that bypasses the input ports and the output ports to recirculate packets within the switch.

### Claim 34 (depends on 33)

The switch of claim 33, further comprising a storage virtual channel coupled to the stash partition.

### Claim 35 (depends on 34)

The switch of claim 34, the storage virtual channel coupling the input buffer to the stash partition.

### Claim 36 (depends on 33)

The switch of claim 33, further comprising logic to selectively enable packets from either the input buffer or from the stash partition to move to the switching fabric.

### Claim 37 (depends on 33)

The switch of claim 33, further comprising a retrieval virtual channel.

### Claim 38 (depends on 37)

The switch of claim 37, the retrieval virtual channel coupling the stash partition to the output buffer.

### Claim 39 (depends on 33)

The switch of claim 33, further comprising logic to implement storage virtual channels and retrieval virtual channels on a plurality of columns of the switching fabric.

### Claim 40 (depends on 33)

The switch of claim 33, further comprising logic to route the packets to the stash partition based on a join-shortest-queue algorithm.

### Claim 41 (depends on 33)

The switch of claim 33, further comprising logic to route the packets to the stash partition based on a credit-based flow control algorithm.

### Claim 42 (depends on 33)

The switch of claim 33, wherein the switch is a crossbar switch.

### Claim 43 (depends on 33)

The switch of claim 33, wherein the switch is part of a dragonfly network.