# US 2021/0344376 A1 · Systems and methods for ultra wideband impulse radio transceivers

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- Number: US 2021/0344376 A1
- Document ID: US20210344376A1
- Status: Published application
- Kind: A1
- Application number: 17/375,456
- Filed: 2021-07-14
- Published: 2021-11-04
- Earliest claimed: 2015-06-01
- Assignees: Transfert Plus, Societe en Commandite
- Applicants: Transfert Plus Societe En Commandite
- Inventors: FREDERIC NABKI; DOMINIC DESLANDES; MOHAMMAD TAHERZADEH-SANI; MICHIEL SOER
- Web page: https://patentgrep.com/patent/US20210344376A1

## CPC

- H04B 1/717: Pulse-related aspects
- H04B 1/1615: {Switching on; Switching off, e.g. remotely (battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34)}
- H04B 1/385: {Transceivers carried on the body, e.g. in helmets}
- H04B 1/7163: using impulse radio
- H04B 1/7183: Synchronisation
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H04L 5/0044: {Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH}
- H04L 7/00: Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)}
- H04L 7/0091: {Transmitter details}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 25/00: Baseband systems
- H04L 25/03834: {using pulse shaping}
- H04L 25/4902: {Pulse width modulation; Pulse position modulation}
- H04L 27/22: Demodulator circuits; Receiver circuits
- H04L 27/2647: {Arrangements specific to the receiver only (equalisation H04L27/01)}
- Y02D 30/70: in wireless communication networks
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

## Claims

### Claim 1

A system for wireless communication comprising:
an ultra-wideband (UWB) transmitter for transmitting data; and
an ultra-wideband (UWB) receiver for receiving data; wherein

### Claim 2 (depends on 1)

The system according to claim 1, wherein
synchronization of at least one of the UWB transmitter and the UWB receiver is established via dedicated synchronization hardware within the electronic device which includes a dual clock timer system; wherein
the dual clock timer system provides ultra-low power consumption during a sleep mode of the at least one of the transmitter and the receiver;
the dual clock timer system comprises a low frequency clock and a base clock generated from the low frequency clock equal to the rate that symbols are processed by at least one of the UWB transmitter and UWB receiver during operation; and
only the low frequency clock of the dual clock timer system is powered during the sleep mode.

### Claim 3 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter and UWB receiver each form part of a common transceiver circuit;
the common transceiver circuit further comprises an integrated DC/DC converter; and
the common transceiver circuit supports at least one of fast circuit start-up and fast circuit shut-down to achieve low power consumption for data rate variations of at least one of 2 orders of magnitude, 3 orders of magnitude, 4 orders of magnitude and greater than 4 orders of magnitude.

### Claim 4 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter and UWB receiver each form part of separate transceivers;
the UWB receiver further comprises an integrated DC/DC converter and a duty cycled receiver circuit;
the UWB transmitter further comprises another integrated DC/DC converter and a duty cycled transmitter circuit; and
each of the duty cycled receiver circuit and the duty cycled transmitter circuit support at least one of fast circuit start-up and fast circuit shut-down to achieve low power consumption for data rate variations of at least one of 2 orders of magnitude, 3 orders of magnitude, 4 orders of magnitude and greater than 4 orders of magnitude.

### Claim 5 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter converts each bit of data to be transmitted to a pulse bundle comprising a plurality of N pulses within the duration of the bit of data where each pulse of the N pulses is at a predetermined frequency of a plurality of M frequencies, has a predetermined amplitude and a predetermined pulse length;
N≥2;
M≥2;
M and N are integers;
the UWB receiver comprises a receiver circuit comprising:
a first squaring circuit down-converts each received pulse of the plurality of N pulses of a received bit into a down-converted frequency range;
a high pass filter removes at least DC content from the down-converted frequency range;
a second squaring circuit; and
an integration circuit; and
the integration circuit integrates the plurality of N pulses of a received bit.

### Claim 6 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises an intermediate frequency (IF) chain that utilizes an instantaneous bandwidth that is on the order of an individual pulse bandwidth whilst the total spectrum covers a much wider bandwidth by exploiting a pulse bundle for each bit;
the pulse bundle for each bit comprises a plurality of N pulses within the duration of the bit of data where each pulse of the N pulses is at a predetermined frequency of a plurality of M frequencies, has a predetermined amplitude and a predetermined pulse length;
N≥2;
M≥2;
M and N are integers; and
the UWB transmitter can reconfigure in real time such that the pulses within a subsequent pulse bundle to a preceding pulse bundle can vary in at least of the number N of pulses, the number M of frequencies, the phases of the plurality of N pulses, the frequencies of the plurality of M frequencies, the amplitudes of the plurality of N pulses and the pulse lengths of the plurality of N pulses.

### Claim 7 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter converts each bit of data to be transmitted to a pulse bundle comprising a plurality of N pulses within the duration of the bit of data where each pulse of the N pulses is at a predetermined frequency of a plurality of M frequencies, has a predetermined amplitude and a predetermined pulse length;
N≥2;
M≥2;
M and N are integers;
the UWB receiver comprises:
an intermedia frequency (IF) receiver stage comprising at least two stages of down-conversion; and
at least one of a high pass and a band-pass filter disposed between each pair of stages of the at least two stages of down-conversion, and
the first stage of each pair of stages of the at least two stages of down-conversion is a squaring stage that translates that an input RF signal spectrum at its input to an output RF signal spectrum that extends down to DC; and
the UWB receiver integrates the plurality of N pulses of a received bit.

### Claim 8 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises:
an intermedia frequency (IF) receiver stage comprising at least two stages of down-conversion; and
at least one of a high pass and a band-pass filter disposed between each pair of stages of the at least two stages of down-conversion, and
the first stage of each pair of stages of the at least two stages of down-conversion is a squaring stage that translates that an input RF signal spectrum at its input to an output RF signal spectrum that extends down to DC.

### Claim 9 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises:
an intermedia frequency (IF) receiver stage comprising at least two stages of down-conversion;
at least one of a high pass and a band-pass filter disposed between each pair of stages of the at least two stages of down-conversion, and
a synchronization circuit comprising a pair of parallel analog-to-digital converter/integrator structures;
the synchronization circuit achieves at least one of faster synchronization and enhanced interference detection; and
the first stage of each pair of stages of the at least two stages of down-conversion is a squaring stage that translates that an input RF signal spectrum at its input to an output RF signal spectrum that extends down to DC;

### Claim 10 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises:
an intermedia frequency (IF) receiver stage comprising at least two stages of down-conversion;
at least one of a high pass and a band-pass filter disposed between each pair of stages of the at least two stages of down-conversion, and
the first stage of each pair of stages of the at least two stages of down-conversion is a squaring stage that translates that an input RF signal spectrum at its input to an output RF signal spectrum that extends down to DC; and
the UWB transmitter and UWB receiver each support on-off keying encoding and pulse-position modulation encoding of data.

### Claim 11 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter and UWB receiver each form part of a common transceiver circuit comprising a clock generator;
the clock generator comprises at least a phase locked loop for generating an output clock signal at a first predetermined frequency;
the phase locked loop comprises a voltage controlled oscillator (VCO), a divider circuit, a phase detector, and a charge pump; wherein
an output of the VCO comprises a clock signal at a second predetermined frequency and is coupled to an output of the clock generator and to an input of the divider circuit;
an output of the divider circuit comprising the clock signal divided in frequency by the divider circuit is coupled to a first input port of the phase detector;
the output clock signal at the second predetermined frequency is coupled to a second input port of the phase detector;
an output of the phase detector comprising pulses generated in dependence upon whether the divided clock is coupled to the charge pump;
the charge pump filters the pulses to generate a control signal for the VCO.

### Claim 12 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter and UWB receiver each form part of separate transceivers;
the UWB transmitter comprises a clock generator;
the clock generator comprises at least a phase locked loop for generating an output clock signal at a first predetermined frequency;
the phase locked loop comprises a voltage controlled oscillator (VCO), a divider circuit, a phase detector, and a charge pump; wherein
an output of the VCO comprises a clock signal at a second predetermined frequency and is coupled to an output of the clock generator and to an input of the divider circuit;
an output of the divider circuit comprising the clock signal divided in frequency by the divider circuit is coupled to a first input port of the phase detector;
the output clock signal at the second predetermined frequency is coupled to a second input port of the phase detector;
an output of the phase detector comprising pulses generated in dependence upon whether the divided clock is coupled to the charge pump;
the charge pump filters the pulses to generate a control signal for the VCO.

### Claim 13 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises a RF signal generator for transmitting data formatted according to a protocol comprising a plurality of frames;
at data rates below a predetermined threshold predetermined portions of the RF signal generator are power cycled to a sleep mode between transmission of each frame of the plurality of frames; and
at data rates above the predetermined threshold the RF signal generator remains on between transmission of each frame of the plurality of frames.

### Claim 14 (depends on 1)

The system according to claim 1, wherein
the UWB receiver receives ultra-wideband wireless signals from the UWB transmitter formatted according to a protocol comprising a plurality of frames;
at data rates below a predetermined threshold predetermined portions of the receiver circuit are power cycled to a sleep mode between receipt of each frame of the plurality of frames; and
at data rates above the predetermined threshold the receiver circuit remains on between transmission of each frame of the plurality of frames.

### Claim 15 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises a control circuit for controlling operation of the UWB transmitter;
the UWB transmitter transmits a data signal according to a protocol comprising a plurality of frames each of a fixed size and a symbol rate;
the control circuit can configure the UWB transmitter to support a plurality of effective data rates by adjusting the length of a sleep period between each frame of the plurality of frames.

### Claim 16 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises a control circuit for controlling operation of the UWB receiver;
the UWB receiver receives a receives the data signal according to a protocol comprising a plurality of frames each of a fixed size and a symbol rate;
the control circuit can configure the UWB receiver to support a plurality of effective data rates by adjusting the length of a sleep period between each frame of the plurality of frames.

### Claim 17 (depends on 1)

The system according to claim 1, wherein
the UWB receiver comprises:
a first portion for processing the received ultra-wideband wireless signals to generate converted received signals; and
a second portion for processing the converted received signals to a plurality of digital signals;
the second portion of the UWB receiver comprises a clock generator for generating a plurality of clock signals and a decision circuit generating the plurality of digital signals in dependence upon the converted received signals and the plurality of clock signals;
the plurality of clock signals are at a frequency determined in dependence upon a symbol rate for bits of data encoded within the ultra-wideband received wireless signals.

### Claim 18 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises a clock generation circuit employing a phase locked loop (PLL) in conjunction with a low frequency oscillator and a pulse generator employing a delay locked loop (DLL);
the UWB transmitter transmits data according to a protocol comprising a plurality of frames;
at data rates below a predetermined threshold the DLL and PLL are power cycled to a sleep mode between transmission of each frame of the plurality of frames whilst the low frequency oscillator remains active; and
at data rates above the predetermined threshold the DLL and PLL remain on between transmission of each frame of the plurality of frames whilst the low frequency oscillator remains active.

### Claim 19 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises:
a pulse pattern block for receiving a clock signal where the pulse pattern block stores a configuration of a plurality of N pulses comprising a symbol pulse bundle employed to represent a current symbol of a data signal being transmitted by the UWB transmitter; and
a clock signal generator for receiving the clock signal and generating a plurality of phased clocks, each phased clock of the plurality of phased clocks having a predetermined phase relationship to the other phased clocks of the plurality of phased clocks and representing the start of a pulse in the symbol pulse bundle;
the plurality of N pulses are transmitted within the duration of the current symbol;
each pulse of the N pulses is at a predetermined frequency of a plurality of M frequencies, has a predetermined amplitude and a predetermined pulse length;
N≥2;
M≥2; and
N and M are integers.

### Claim 20 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises:
a pulse pattern block for receiving a clock signal where the pulse pattern block stores a plurality of configurations, each configuration defining a symbol pulse bundle comprising a plurality of pulses to be transmitted by the UWB transmitter which represent a current symbol of data being transmitted;
a clock signal generator receiving the clock signal and generating a plurality of phased clocks, each phased clock of the plurality of phased clocks having a predetermined phase relationship to the other phased clocks of the plurality of phased clocks and representing the start of a pulse in the symbol pulse bundle;
a multiplexer for receiving the plurality of phased clocks from the clock signal generator and selecting from the pulse pattern block a pulse configuration of the configuration of the plurality of configurations where the pulse configuration relates to a current pulse of the symbol pulse bundle representing the current symbol of data being transmitted;
a pulse generator coupled to the multiplexer for generating an enable pulse with a pulse width set by the pulse configuration selected for the current pulse of the symbol pulse bundle where the enable pulse enables a digitally controlled oscillator (DCO); and
the DCO also coupled to the multiplexer for generating pulses of a predetermined shape where the frequency of each pulse is set by the pulse configuration of the configuration of the plurality of configurations for the current pulse of the symbol pulse bundle when the DCO is enabled by the enable pulse from the pulse generator; and
the pulse pattern block is dynamically updated during generation of the transmission signal; and
the configuration of the plurality of configurations can be changed between the current symbol of data being transmitted and the next symbol of data to be transmitted.

### Claim 21 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises:
an amplifier comprising:
an input port for receiving a pulse to be amplified;
a ground node for receiving a shaping signal;
a pair of coupled transistors having their sources coupled to the ground node and their drains connected to a power supply;
a third transistor having its drain coupled to the ground node and to ground via a capacitor, its source coupled to ground and its gate coupled to the ground node;
a first clock input port for receiving a first clock signal coupled to a gate of one transistor of the pair of transistors;
a second clock input port for receiving a second clock signal coupled to a gate of the other transistor of the pair of transistors.

### Claim 22 (depends on 21)

The system according to claim 21, wherein
the shaping signal comprises a shaping pulse which is applied to the gate of the third transistor;
the shaping pulse defines the duration of an output pulse from the amplifier comprising the amplified pulse; and
the third transistor and capacitor shape the pulse of the shaping signal applied to the ground node such that the amplifier generates the amplified pulse with a Gaussian profile.

### Claim 23 (depends on 1)

The system according to claim 1, wherein
the UWB transmitter comprises a clock generation circuit comprising:
a low frequency oscillator generating a sinusoidal oscillator signal at a first predetermined frequency;
a converter circuit for converting the sinusoidal oscillator signal at the first predetermined frequency to a square wave clock at the first predetermined frequency; and
a phase locked loop for generating an output clock signal at a second predetermined frequency; and
the clock generation circuit generates a base clock equal to the symbol frequency of data to be transmitted by the UWB transmitter;
the UWB transmitter converts each bit of data to be transmitted to a pulse bundle comprising a plurality of N pulses within the duration of the bit of data defined by the base clock where each pulse of the N pulses is at a predetermined frequency of a plurality of M frequencies, has a predetermined amplitude and a predetermined pulse length;
N≥2;
M≥2;
M and N are integers.