# US 2021/0344358 A1 · Processing-in-memory (pim) devices

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- Number: US 2021/0344358 A1
- Document ID: US20210344358A1
- Status: Published application
- Kind: A1
- Application number: 17/375,692
- Filed: 2021-07-14
- Published: 2021-11-04
- Earliest claimed: 2019-09-23
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Choung Ki SONG
- Web page: https://patentgrep.com/patent/US20210344358A1

## CPC

- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/063: using electronic means
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/098: {using single parity bit}
- H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- G06F 2207/4824: Neural networks
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate write data and a write fail check signal from write input data when a write operation in an operation mode is performed, and generate a fail flag signal and converted data from read data and a read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data, based on the fail flag signal to generate MAC operation result data.

## Claims

### Claim 1

A processing-in-memory (PIM) device comprising:
a cyclic redundancy checking (CRC) logic circuit configured to generate write data and a write fail check signal from write input data when a write operation in an operation mode is performed, and generate a fail flag signal and converted data from read data and a read fail check signal when a read operation in the operation mode is performed; and
a multiplication and accumulation (MAC) operator configured to perform a MAC arithmetic operation for the converted data and buffer data, based on the fail flag signal to generate MAC operation result data.

### Claim 2 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit receives the write input data input through a data input/output circuit when the write operation in an operation mode is performed through a data line.

### Claim 3 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit removes one or more bits included in the write input data, and generates the write data, based on the remaining bits when the write operation in the operation mode is performed.

### Claim 4 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit removes at least one bit from bits included in a mantissa part of the write input data when the write input data is implemented in a floating-point method and generates the write data from the write input data having the mantissa part including the remaining bits when the write operation in the operation mode is performed.

### Claim 5 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit removes at least one bit from bits included in the mantissa part of the write input data when the write input data is implemented in a floating-point method, the bit combination of the remaining bits is adjusted by rounding methods according to the removed bit, and the write data is generated from the write input data having the mantissa part including the bits with a bit combination that has been adjusted, when the write operation in the operation mode is performed.

### Claim 6 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit removes at least one bit from bits included in an exponent part of the write input data when the write input data is implemented in a floating-point method, and generates the write data from the write input data having the exponent part including the remaining bits, when the write operation in the operation mode is performed.

### Claim 7 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit removes at least one bit from bits included in the exponent part of the write input data when the write input data is implemented in a floating-point method, a bit combination of the remaining bits is adjusted to a preset bit combination according to the removed bit, and the write data is generated from the write input data having the exponent part including the bits with a bit combination that has been adjusted, when the write operation in the operation mode is performed.

### Claim 8 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit encodes the write data, based on cyclic redundancy check (CRC) to generate the write fail check signal when the write operation in the operation mode is performed.

### Claim 9 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit adds ‘0’ to the write data as many as the number of bits less than the number of bits of a divisor code by one bit, and generates a remainder calculated when the write data to which ‘0’ is added is divided by the divisor code as the write fail check signal.

### Claim 10 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit decodes the read data and the read fail check signal, based on cyclic redundancy check (CRC) to generate the fail flag signal when the read operation in the operation mode is performed.

### Claim 11 (depends on 10)

The PIM device of claim 10, wherein the CRC logic circuit divides the read data and the read fail check signal by a divisor code to generate the fail flag signal.

### Claim 12 (depends on 10)

The PIM device of claim 10, wherein the CRC logic circuit adds preset bits to the read data to generate the converted data when the read operation in the operation mode is performed.

### Claim 13 (depends on 12)

The PIM device of claim 12, wherein the CRC logic circuit adds the preset bits to a mantissa part of the read data to generate the converted data when the read data is implemented in a floating-point method.

### Claim 14 (depends on 12)

The PIM device of claim 12, wherein the CRC logic circuit adds the preset bits to an exponent part of the read data to generate the converted data when the read data is implemented in a floating-point method.

### Claim 15 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit applies the write data and the write fail check signal to the storage region when the write operation in the operation mode is performed, and receives the read data and the read fail check signal when the read operation in the operation mode is performed.

### Claim 16 (depends on 15)

The PIM device of claim 15, wherein the storage region outputs the write data and the write fail check signal stored when the write operation in the operation mode is performed as the read data and the read fail check signal, when the read operation in the operation mode is performed.

### Claim 17 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit includes:
a write data generator configured to generate the write data from the write input data when the write operation in the operation mode is performed; and
a write fail check signal generator configured to encode the write data to generate the write fail check signal when the write operation in the operation mode is performed.

### Claim 18 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit includes:
a fail flag signal generator configured to decode the read data and the read fail check signal to generate the fail flag signal when the read operation in the operation mode is performed; and
a converted data generator configured to generate the converted data, based on the read data when the read operation in the operation mode is performed.

### Claim 19 (depends on 1)

The PIM device of claim 1, wherein the MAC operator performs a MAC arithmetic operation for the converted data, which is weight data applied to a neural network circuit and the buffer data, which is vector data applied to the neural network circuit.

### Claim 20 (depends on 1)

The PIM device of claim 1, wherein the CRC logic circuit generates the fail flag signal activated when an error is included in the read data.

### Claim 21 (depends on 20)

The PIM device of claim 20, wherein the MAC operator is configured so that at least one of a multiplication operation and an addition operation included in the MAC arithmetic operation is not performed when the fail flag signal is activated.

### Claim 22

A processing-in-memory (PIM) device comprising:
a storage region configured to receive and store write data and a write fail check signal when a write operation in an operation mode is performed and output read data and a read fail check signal when a read operation in the operation mode is performed; and
a cyclic redundancy checking (CRC) logic circuit configured to generate the write data and the write fail check signal from write input data when the write operation in the operation mode is performed, and generate converted data for a multiplication and accumulation (MAC) arithmetic operation from the read data and the read fail check signal when the read operation in the operation mode is performed.

### Claim 23 (depends on 22)

The PIM device of claim 22, wherein the storage region outputs the write data and write fail check signal stored when the write operation in the operation mode is performed as the read data and the read fail check signal, when the read operation in the operation mode is performed.

### Claim 24 (depends on 22)

The PIM device of claim 22, wherein the CRC logic circuit generates the converted data, which is weight data applied to a neural network circuit.

### Claim 25 (depends on 22)

The PIM device of claim 22, wherein the CRC logic circuit generates the converted data, which is vector data applied to a neural network circuit.