# US 2021/0344357 A1 · Processing-in-memory (pim) devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0344357 A1 - Document ID: US20210344357A1 - Status: Published application - Kind: A1 - Application number: 17/375,622 - Filed: 2021-07-14 - Published: 2021-11-04 - Earliest claimed: 2019-09-23 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Choung Ki SONG - Web page: https://patentgrep.com/patent/US20210344357A1 ## CPC - G11C 29/42: using error correcting codes [ECC] or parity check - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06N 3/063: using electronic means - H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit - H03M 13/098: {using single parity bit} - H03M 13/1575: {Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance} - H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes - G06F 2207/4824: Neural networks - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data. ## Claims ### Claim 1 A processing-in-memory (PIM) device comprising: an error correction code (ECC) logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a multiplication and accumulation (MAC) operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data. ### Claim 2 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit receives the first write input data and the second write input data input through a data input/output circuit when the write operation in the operation mode is performed through a data line. ### Claim 3 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit removes one or more bits included in the first write input data and the second write input data and generates the first write data and the second write data, based on the remaining bits when the write operation in the operation mode is performed. ### Claim 4 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit removes at least one bit from bits included in a mantissa part of each piece of the first write input data and the second write input data and generates the first write data and the second write data from the first write input data and the second write input data respectively having the mantissa part including the remaining bits when each piece of the first write input data and the second write input data is implemented in a floating-point method, when the write operation in the operation mode is performed. ### Claim 5 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit removes at least one bit from bits included in the mantissa part of each piece of the first write input data and the second write input data when each piece of the first write input data and the second write input data is implemented in a floating-point method, the bit combination of the remaining bits is adjusted by rounding methods according to the removed bit, and the first write data and the second write data are generated from the first write input data and the second write input data respectively having the mantissa part including the bits with a bit combination that has been adjusted, when the write operation in the operation mode is performed. ### Claim 6 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit removes at least one bit from bits included in an exponent part of each piece of the first write input data and the second write input data when each piece of the first write input data and the second write input data is implemented in a floating-point method, and generates the first write data and the second write data from the first write input data and the second write input data respectively having the exponent part including the remaining bits, when the write operation in an operation mode is performed. ### Claim 7 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit removes at least one bit from bits included in the exponent part of each piece of the first write input data and the second write input data when each piece of the first write input data and the second write input data is implemented in a floating-point method, the bit combination of the remaining bits is adjusted to a preset bit combination according to the removed bit, and the first write data and the second write data are generated from the first write input data and the second write input data respectively having the exponent part including bits with a bit combination that has been adjusted, when the write operation in the operation mode is performed. ### Claim 8 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit encodes the first write data to generate the first write parity and encodes the second write data to generate the second write parity when the write operation in the operation mode is performed. ### Claim 9 (depends on 8) The PIM device of claim 8, wherein the ECC logic circuit encodes the first write data, based on a Hamming code to generate the first write parity, and encodes the second write data, based on the Hamming code to generate the second write parity. ### Claim 10 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit decodes the first read data and the first read parity to generate first syndrome when the read operation in the operation mode is performed, and decodes the second read data and the second read parity to generate second syndrome when the read operation in the operation mode is performed. ### Claim 11 (depends on 10) The PIM device of claim 10, wherein the ECC logic circuit decodes the first read data and the first read parity, based on a Hamming code to generate the first syndrome, and decodes the second read data and the second read parity, based on the Hamming code to generate the second syndrome. ### Claim 12 (depends on 10) The PIM device of claim 10, wherein the ECC logic circuit corrects an error included in the first read data, based on the first syndrome to generate the first corrected read data when the read operation in the operation mode is performed, and corrects an error included in the second read data, based on the second syndrome to generate the second corrected read data when the read operation in the operation mode is performed. ### Claim 13 (depends on 12) The PIM device of claim 12, wherein the ECC logic circuit adds preset bits to the first corrected read data to generate the first converted data when the read operation in the operation mode is performed, and adds preset bits to the second corrected read data to generate the second converted data when the read operation in the operation mode is performed. ### Claim 14 (depends on 13) The PIM device of claim 13, wherein the ECC logic circuit adds the preset bits to a mantissa part of each piece of the first corrected read data and the second corrected read data to generate the first converted data and the second converted data when each piece of the first corrected read data and the second corrected read data is implemented in a floating-point method. ### Claim 15 (depends on 13) The PIM device of claim 13, wherein the ECC logic circuit adds the preset bits to an exponent part of each piece of the first corrected read data and the second corrected read data to generate the first converted data and the second converted data when each piece of the first corrected read data and the second corrected read data is implemented in a floating-point method. ### Claim 16 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit applies the first write data, the first write parity, the second write data, and the second write parity to the storage region when the write operation in the operation mode is performed, and receives the first read data, the first read parity, the second read data, and the second read parity when the read operation in the operation mode is performed. ### Claim 17 (depends on 16) The PIM device of claim 16, wherein the storage region outputs the first write data, the second, the second write data, and the second write parity write parity stored when the write operation in the operation mode is performed as the first read data, the first read parity, the second read data, and the second read parity when the read operation in the operation mode is performed. ### Claim 18 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit includes: a write data generator configured to generate the first write data and the second write data from the first write input data and the second write input data when the write operation in the operation mode is performed; and a write parity generator configured to encode the first write data and the second write data to generate the first write parity and the second write parity when the write operation in the operation mode is performed. ### Claim 19 (depends on 1) The PIM device of claim 1, wherein the ECC logic circuit includes: a syndrome generator configured to decode the first read data and the first read parity to generate first syndrome and decode the second read data and the second read parity to generate second syndrome when the read operation in the operation mode is performed; a corrected read data generator configured to correct an error included in the first read data, based on the first syndrome to generate the first corrected read data and correct an error included in the second read data, based on the second syndrome to generate the second corrected read data when the read operation in the operation mode is performed; and a converted data generator configured to generate the first converted data and the second converted data, based on the first corrected read data and the second corrected read data when the read operation in the operation mode is performed. ### Claim 20 (depends on 1) The PIM device of claim 1, wherein the MAC operator performs a MAC arithmetic operation for the first converted data, which is weight data applied to a neural network circuit and the second converted data, which is vector data applied to the neural network circuit. ### Claim 21 (depends on 1) The PIM device of claim 1, wherein the MAC operator performs a MAC arithmetic operation for the first converted data, which is vector data applied to a neural network circuit and the second converted data, which is weight data applied to the neural network circuit. ### Claim 22 A processing-in-memory (PIM) device comprising: a storage region configured to receive and store first write data, first write parity, second write data, and second write parity when a write operation in an operation mode is performed, and output first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and an error correction code (ECC) logic circuit configured to generate the first write data, the first write parity, the second write data, and the second write parity from first write input data and second write input data when the write operation in the operation mode is performed, and generate first converted data and second converted data from the first read data, the first read parity, the second read data, and the second read parity when the read operation in the operation mode is performed. ### Claim 23 (depends on 22) The PIM device of claim 22, wherein the storage region outputs the first write data, the first write parity, the second write data, and the second write parity stored when the write operation in the operation mode is performed as the first read data, the first read parity, the second read data, and the second read parity when the read operation in the operation mode is performed. ### Claim 24 (depends on 22) The PIM device of claim 22, wherein the ECC logic circuit generates the first converted data, which is weight data applied to a neural network circuit and generates the second converted data, which is vector data applied to the neural network circuit. ### Claim 25 (depends on 22) The PIM device of claim 22, wherein the ECC logic circuit generates the first converted data, which is vector data applied to a neural network circuit and generates the second converted data, which is weight data applied to the neural network circuit.