# US 2021/0344352 A1 · Memory controller and method of data bus inversion using an error detection correction code

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- Number: US 2021/0344352 A1
- Document ID: US20210344352A1
- Status: Published application
- Kind: A1
- Application number: 17/321,060
- Filed: 2021-05-14
- Published: 2021-11-04
- Earliest claimed: 2014-12-10
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; John Eric Linstadt
- Web page: https://patentgrep.com/patent/US20210344352A1

## CPC

- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0673: {Single storage device}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 13/1668: {Details of memory controller}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/151: {using error location or error correction polynomials}
- H03M 13/1515: {Reed-Solomon codes}
- H03M 13/19: Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

## Claims

### Claim 1

(canceled)

### Claim 2

A memory module, comprising:
a substrate;
multiple memory devices disposed on the substrate;
a multi-bit data interface including multiple data pins defining a multi-bit width;
the multiple memory devices to receive write data bits from a memory controller via the multi-bit data interface, the write data bits selectively inverted by the memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
the multiple memory devices to store the selectively inverted write data bits; and
the multiple memory devices to transmit the selectively inverted write data bits as read data to the memory controller via the multiple data pins in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.

### Claim 3 (depends on 2)

The memory module according to claim 2, wherein the write data bits selectively inverted by the memory controller are received as encoded write data in accordance with an error detection/correction (EDC) code, the encoded write data including first error information associated with the write data bits.

### Claim 4 (depends on 3)

The memory module according to claim 3, wherein the EDC code enables detection of a first class of errors, and correction of a second class of errors.

### Claim 5 (depends on 3)

The memory module according to claim 3, wherein:
the multi-bit data interface defines at least a 72-bit width; and
the EDC code includes symbols that each have a group of four data bits.

### Claim 6 (depends on 5)

The memory module according to claim 5, wherein the EDC code comprises a Chipkill EDC code.

### Claim 7 (depends on 3)

The memory module according to claim 3, wherein:
the first error information is transmitted by the multiple memory devices with the read data in response to the read command; and
wherein an indication of whether the read data is DBI-encoded is based on the first error information.

### Claim 8 (depends on 2)

The memory module according to claim 2, embodied as a dynamic random access (DRAM) memory module.

### Claim 9

A method of operation in a memory module, the memory module including multiple memory devices disposed on a substrate, the method comprising:
receiving, at the memory module, write data bits from a memory controller, the write data bits received as selectively inverted by the memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
storing, in each of the multiple memory devices, respective portions of the selectively inverted write data bits; and
transmitting, from each of the multiple memory devices, the respective portions of the selectively inverted write data bits as read data to the memory controller in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.

### Claim 10 (depends on 9)

The method of claim 9, wherein the receiving of the write data bits from the memory controller further comprises:
receiving the write data bits further encoded by the memory controller in accordance with an error detection/correction (EDC) code to generate first error information.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
receiving the first error information from the memory controller.

### Claim 12 (depends on 10)

The method of claim 10, wherein the EDC code enables detection of a first class of errors, and correction of a second class of errors.

### Claim 13 (depends on 10)

The method of claim 10, wherein the EDC code comprises a Chipkill EDC code.

### Claim 14 (depends on 10)

The method of claim 10, wherein the transmitting further comprises:
transmitting, from each of the multiple memory devices, respective portions of the first error information with corresponding portions of the read data in response to the read command; and
wherein an indication of whether the read data is DBI-encoded is based on the first error information.

### Claim 15

A dynamic random access memory (DRAM) memory module comprising:
a substrate;
multiple DRAM integrated circuit (IC) memory devices disposed on the substrate;
a multi-bit data interface including multiple data pins defining a multi-bit width;
the multiple memory devices to receive write data bits from a DRAM IC memory controller via the multi-bit data interface, the write data bits selectively inverted by the DRAM IC memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
the multiple DRAM IC memory devices to store the selectively inverted write data bits; and
the multiple DRAM IC memory devices to transmit the selectively inverted write data bits as read data to the DRAM IC memory controller via the multiple data pins in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.

### Claim 16 (depends on 15)

The DRAM memory module according to claim 15, wherein the write data bits selectively encoded by the DRAM IC memory controller are further encoded by the DRAM IC memory controller in accordance with an error detection/correction (EDC) code to generate first error information.

### Claim 17 (depends on 16)

The DRAM memory module according to claim 16, wherein the EDC code enables detection of a first class of errors, and correction of a second class of errors.

### Claim 18 (depends on 17)

The DRAM memory module according to claim 17, wherein:
the multi-bit data interface defines a 72-bit width.

### Claim 19 (depends on 18)

The DRAM memory module according to claim 18, wherein the EDC code includes symbols that each have a group of four data bits.

### Claim 20 (depends on 16)

The DRAM memory module according to claim 16, wherein the EDC code comprises a Chipkill EDC code.

### Claim 21 (depends on 16)

The DRAM memory module according to claim 16, wherein:
the first error information is transmitted by the multiple DRAM IC memory devices with the read data in response to the read command; and
wherein an indication of whether the read data is DBI-encoded is based on the first error information.